STRUCT STM32_SPI_REGSPEC(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

✨ struct stm32_spi_regspec(9) ✨

okay so bestie, we're in the Kernel API Manual today and the vibe is registers πŸ’… this one is literally the struct that holds all the stm32 register definitions, and it's compatible dependent data β€” meaning the layout changes depending on which chip you're on, iykyk πŸ¦‹


πŸŽ€ NAME πŸŽ€

struct stm32_spi_regspec β€” the stm32 registers definition, aka the compatible-dependent data that tells the driver where everything lives 🫢


✨ SYNOPSIS ✨

struct stm32_spi_regspec {
    const struct stm32_spi_reg en;
    const struct stm32_spi_reg dma_rx_en;
    const struct stm32_spi_reg dma_tx_en;
    const struct stm32_spi_reg cpol;
    const struct stm32_spi_reg cpha;
    const struct stm32_spi_reg lsb_first;
    const struct stm32_spi_reg cs_high;
    const struct stm32_spi_reg br;
    const struct stm32_spi_reg rx;
    const struct stm32_spi_reg tx;
    const struct stm32_spi_reg fullcfg;
    const struct stm32_spi_reg rdy_en;
};

like, every single field is a const struct stm32_spi_reg β€” no cap, it's giving "one type, twelve little homes" 🏠✨


πŸ‘‘ Members πŸ‘‘

okay so here's the whole squad, field by field, no skips fr fr:

  • en β€” the enable register and the SPI enable bit 🎚️
  • dma_rx_en β€” the SPI DMA RX enable register end the SPI DMA RX enable bit (yes, "end" β€” that's what the page says, we don't edit the source 😭)
  • dma_tx_en β€” the SPI DMA TX enable register end the SPI DMA TX enable bit
  • cpol β€” the clock polarity register and the polarity bit 🌊
  • cpha β€” the clock phase register and the phase bit
  • lsb_first β€” the LSB transmitted first register and its bit πŸ”„
  • cs_high β€” chips select active value 🎯
  • br β€” the baud rate register and bitfields πŸš€
  • rx β€” the SPI RX data register πŸ“₯
  • tx β€” the SPI TX data register πŸ“€
  • fullcfg β€” the SPI full or limited feature set register (the feature-set vibe check πŸ’€)
  • rdy_en β€” the SPI ready feature register ⭐

🌈 SEE ALSO 🌈

Kernel file ./drivers/spi/spi-stm32.c β€” plus this whole friend group of cross-references, all of them, exactly as listed 🫢

struct stm32_spi_reg(9), struct stm32_spi_cfg(9), struct stm32_spi(9), stm32h7_spi_get_fifo_size(9), stm32f4_spi_get_bpw_mask(9), stm32f7_spi_get_bpw_mask(9), stm32h7_spi_get_bpw_mask(9), stm32mp25_spi_get_bpw_mask(9), stm32_spi_prepare_mbr(9), stm32h7_spi_prepare_fthlv(9), stm32f4_spi_write_tx(9), stm32f7_spi_write_tx(9), stm32h7_spi_write_txfifo(9), stm32f4_spi_read_rx(9), stm32f7_spi_read_rx(9), stm32h7_spi_read_rxfifo(9), stm32_spi_enable(9), stm32fx_spi_disable(9), stm32h7_spi_disable(9), stm32_spi_can_dma(9), stm32fx_spi_irq_event(9), stm32fx_spi_irq_thread(9), stm32h7_spi_irq_thread(9), stm32_spi_prepare_msg(9), stm32fx_spi_dma_tx_cb(9), stm32_spi_dma_rx_cb(9), stm32_spi_dma_config(9), stm32fx_spi_transfer_one_irq(9), stm32h7_spi_transfer_one_poll(9), stm32h7_spi_transfer_one_irq(9), stm32fx_spi_transfer_one_dma_start(9), stm32f7_spi_transfer_one_dma_start(9), stm32h7_spi_transfer_one_dma_start(9), stm32_spi_prepare_rx_dma_mdma_chaining(9), stm32_spi_transfer_one_dma(9), stm32f4_spi_set_bpw(9), stm32f7_spi_set_bpw(9), stm32h7_spi_set_bpw(9), stm32_spi_set_mbr(9), stm32_spi_communication_type(9), stm32fx_spi_set_mode(9), stm32h7_spi_set_mode(9), stm32h7_spi_data_idleness(9), stm32h7_spi_number_of_data(9), stm32_spi_transfer_one_setup(9), stm32_spi_can_poll(9), stm32_spi_transfer_one(9), stm32_spi_unprepare_msg(9), stm32fx_spi_config(9), stm32h7_spi_config(9)

lowkey iconic how many of these there are β€” go read them all, bestie, I believe in you 🧚

okay that's the whole page!! this lil beauty lives over in ./drivers/spi, it's dated October 2026, and it's filed under struct stm32_spi_regspec(9). slay, go write some SPI drivers πŸ’–πŸŽ€πŸ¦‹

πŸ“¦ where this page comes from