STRUCT SPI_TRANSFER_HEAD(9)

🎀 NAME

Okay so welcome to the Kernel API Manual, bestie 💖 — this is the page for struct spi_transfer_head(9), aka the virtio SPI transfer descriptor. No cap, that’s the whole vibe of this struct. 🦋

✨ SYNOPSIS

struct spi_transfer_head {
    __u8 chip_select_id;
    __u8 bits_per_word;
    __u8 cs_change;
    __u8 tx_nbits;
    __u8 rx_nbits;
    __u8 reserved[3];
    __le32 mode;
    __le32 freq;
    __le32 word_delay_ns;
    __le32 cs_setup_ns;
    __le32 cs_delay_hold_ns;
    __le32 cs_change_delay_inactive_ns;
};

💅 Members

Here’s the field-by-field tea, bestie — every single one, in order. 🫶

• chip_select_id — the chipselect index the SPI transfer used. 💅
• bits_per_word — the number of bits in each SPI transfer word. ✨
• cs_change — whether to deselect device after finishing this transfer before starting the next transfer; 0 means cs keep asserted and 1 means cs deasserted then asserted again. 🎀
• tx_nbits — bus width for write transfer. The values are:
  • 0,1: bus width is 1, also known as SINGLE.
  • 2: bus width is 2, also known as DUAL.
  • 4: bus width is 4, also known as QUAD.
  • 8: bus width is 8, also known as OCTAL.
  • other values are invalid.
• rx_nbits — bus width for read transfer. The values are:
  • 0,1: bus width is 1, also known as SINGLE.
  • 2: bus width is 2, also known as DUAL.
  • 4: bus width is 4, also known as QUAD.
  • 8: bus width is 8, also known as OCTAL.
  • other values are invalid.
• reserved — for future use. 🦋
• mode — SPI transfer mode. Here’s the bit-by-bit tea, highkey important:
  • bit 0: CPHA, determines the timing (i.e. phase) of the data bits relative to the clock pulses. For CPHA=0, the "out" side changes the data on the trailing edge of the preceding clock cycle, while the "in" side captures the data on (or shortly after) the leading edge of the clock cycle. For CPHA=1, the "out" side changes the data on the leading edge of the current clock cycle, while the "in" side captures the data on (or shortly after) the trailing edge of the clock cycle.
  • bit 1: CPOL, determines the polarity of the clock. CPOL=0 is a clock which idles at 0, and each cycle consists of a pulse of 1. CPOL=1 is a clock which idles at 1, and each cycle consists of a pulse of 0.
  • bit 2: CS_HIGH, if 1, chip select active high, else active low.
  • bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB first, else LSB first.
  • bit 4: LOOP, loopback mode.
• freq — the transfer speed in Hz. ⚡
• word_delay_ns — delay to be inserted between consecutive words of a transfer, in ns unit. 🌸
• cs_setup_ns — delay to be introduced after CS is asserted, in ns unit. 💜
• cs_delay_hold_ns — delay to be introduced before CS is deasserted for each transfer, in ns unit. 💖
• cs_change_delay_inactive_ns — delay to be introduced after CS is deasserted and before next asserted, in ns unit. ✨

🦋 SEE ALSO

Kernel file ./include/uapi/linux/virtio_spi.h struct virtio_spi_config(9), struct spi_transfer_result(9) 👑

🫶 signing off from ./include/uapi/linux, October 2026, with struct spi_transfer_head(9) — mwah 💋✨