STRUCT SG2042_DIVIDER_CLOCK(9)

✨ struct sg2042_divider_clock(9) ✨

okay bestie, welcome to the Kernel API Manual page for struct sg2042_divider_clock — yes it's a divider clock, yes it's giving clock-framework-core, and yes we're gonna get through it together 💅

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🌸 NAME 🌸

struct sg2042_divider_clock — the divider clock, periodt. That's literally the whole vibe. A clock that divides. Iconic of it honestly 🎀

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🦋 SYNOPSIS 🦋

struct sg2042_divider_clock {
    struct clk_hw hw;
    unsigned int id;
    void __iomem *reg;
    spinlock_t *lock;
    u32 offset_ctrl;
    u8 shift;
    u8 width;
    u8 div_flags;
    u32 initval;
 };

like, that's the whole struct, no crumbs left behind 🫶 copy it exactly, don't be cute with it.

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👑 Members 👑

so every field in this struct has a whole personality, let's meet them one by one:

• hw — the clk_hw for initialization. it's the main character that lets the clock framework even know this thing exists 💫
• id — used to map clk_onecell_data. it's the little name tag so everything ends up in the right spot 🔖
• reg — used for readl/writel. NOTE: DIV registers are ALL in CLOCK! like, all of them, no exceptions, don't go looking elsewhere 😭
• lock — a spinlock to protect register access. modification of frequency can only be served one at the time, so bestie, please wait your turn 🙈
• offset_ctrl — offset of divider control registers. it tells you where the party's at 📍
• shift — shift of "Clock Divider Factor" in divider control register. it's how far left you gotta slide ✨
• width — width of "Clock Divider Factor" in divider control register. how many bits the factor gets to take up, no more no less 📏
• div_flags — private flags for this clock, not for framework-specific. just this clock's own personal business, ok? 💅
• initval — lowkey the most dramatic member, so listen up 🍓

In the divider control register, we can configure whether to use the value of "Clock Divider Factor" or just use the initial value pre-configured by IC. BIT[3] controls this and by default (value is 0), means initial value is used.

NOTE that we cannot read the initial value (default value when poweron) and default value of "Clock Divider Factor" is zero, which I think is a hardware design flaw and should be sync-ed with the initial value.

so in software we have to add a configuration item (initval) to manually configure this value and use it when BIT[3] is zero. that's it, that's the whole sad little workaround 😭 hardware really said "figure it out" and software said "fine, bet" 🔥

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🌈 SEE ALSO 🌈

• Kernel file ./drivers/clk/sophgo/clk-sg2042-clkgen.c
• struct sg2042_gate_clock(9)
• struct sg2042_mux_clock(9)

go read those too, they're the rest of the squad, iykyk 👑

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aaaand that's the page, bestie!! 🧚 you made it all the way through a struct with nine whole members, no cap, very proud of you 🫶

signed off with love from ./drivers/clk/sophgo, dated October 2026, and yes we are still absolutely talking about struct sg2042_divider_clock(9) — the icon, the legend, the divider 💜