STRUCT RZG2L_CPG_INFO(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– struct_rzg2l_cpg_info(9) β€” SoC-specific CPG Description πŸ’–

okay so bestie, welcome to the Kernel API Manual ✨ this one's literally about struct rzg2l_cpg_info, aka the SoC-specific CPG Description. it's giving "one struct to describe a whole SoC's clock pulse generator situation" and honestly? iconic. πŸŽ€


🌸 NAME 🌸

struct rzg2l_cpg_info β€” the SoC-specific CPG Description, no cap πŸ’…


✨ SYNOPSIS ✨

like, here's the whole vibe, character for character, don't touch a single glyph:

struct rzg2l_cpg_info {
    const struct cpg_core_clk *core_clks;
    unsigned int num_core_clks;
    unsigned int last_dt_core_clk;
    unsigned int num_total_core_clks;
    const struct rzg2l_mod_clk *mod_clks;
    unsigned int num_mod_clks;
    unsigned int num_hw_mod_clks;
    const unsigned int *no_pm_mod_clks;
    unsigned int num_no_pm_mod_clks;
    const struct rzg2l_reset *resets;
    unsigned int num_resets;
    const unsigned int *crit_mod_clks;
    unsigned int num_crit_mod_clks;
    const unsigned int *crit_resets;
    unsigned int num_crit_resets;
    bool has_clk_mon_regs;
 };

lowkey a lot of fields but we're gonna go through every single one, bestie, no skips 🫢


πŸ¦‹ Members πŸ¦‹

  • core_clks β€” the array of Core Clock definitions 🌟 like the guest list, but for clocks.
  • num_core_clks β€” how many entries are actually chillin' in core_clks[] πŸ”’
  • last_dt_core_clk β€” the ID of the last Core Clock that got exported to DT πŸ‘‘
  • num_total_core_clks β€” the total number of Core Clocks (that's exported plus internal, so yes, both) πŸ’―
  • mod_clks β€” the array of Module Clock definitions 🧚
  • num_mod_clks β€” how many entries live in mod_clks[] πŸ”’
  • num_hw_mod_clks β€” the number of Module Clocks that are actually supported by the hardware πŸ’€ (the hardware said what it said)
  • resets β€” the array of Module Reset definitions πŸ”„
  • num_resets β€” number of entries in resets[] πŸ”’
  • crit_mod_clks β€” an array holding the Module Clock IDs of critical clocks that should not be disabled without a knowledgeable driver 😭 like fr fr, don't just go disabling these, you need someone who actually knows what they're doing.
  • num_crit_mod_clks β€” number of entries in crit_mod_clks[] πŸ”’
  • crit_resets β€” an array holding the Reset IDs of critical resets that should not be asserted without a knowledgeable driver πŸ™ˆ same energy, same warning β€” knowledgeable driver required, periodt.
  • num_crit_resets β€” number of entries in crit_resets[] πŸ”’
  • has_clk_mon_regs β€” a bool flag saying whether this SoC has CLK_MON registers or not ⭐ simple as that, queen.

🌈 SEE ALSO 🌈

  • Kernel file ./drivers/clk/renesas/rzg2l-cpg.h
  • struct rzg2l_mod_clk(9)
  • struct rzg2l_reset(9)

go read those next, iykyk πŸ¦‹


and that's the whole page, bestie!! πŸ’– this cutie lives under ./drivers/clk/renesas, it's dated October 2026, and it's serving struct rzg2l_cpg_info(9) realness from the Kernel API Manual. slay, ate, no crumbs. πŸ‘‘βœ¨πŸŽ€

πŸ“¦ where this page comes from