STRUCT ROCKCHIP_PLL_CLOCK(9)

🌸 NAME 🌸

okay so bestie, welcome to the Kernel API Manual page for struct rockchip_pll_clock — literally information about pll clock 💖. Like, this struct is the main character when you need the deets on a pll clock, no cap.

✨ SYNOPSIS ✨

struct rockchip_pll_clock {
    unsigned int            id;
    const char              *name;
    const char              *const *parent_names;
    u8 num_parents;
    unsigned long           flags;
    int con_offset;
    int mode_offset;
    int mode_shift;
    int lock_shift;
    enum rockchip_pll_type  type;
    u8 pll_flags;
    struct rockchip_pll_rate_table *rate_table;
};

🎀 Members 🎀

• id — platform specific id of the clock. iykyk.
• name — name of this pll clock. slay.
• parent_names — name of the parent clock.
• num_parents — number of parents.
• flags — optional flags for basic clock.
• con_offset — offset of the register for configuring the PLL.
• mode_offset — offset of the register for configuring the PLL-mode.
• mode_shift — offset inside the mode-register for the mode of this pll.
• lock_shift — offset inside the lock register for the lock status.
• type — Type of PLL to be registered.
• pll_flags — hardware-specific flags.
• rate_table — Table of usable pll rates.

💅 Description 💅

okay so the Flags: are giving very specific energy, and here's exactly what they mean:

• ROCKCHIP_PLL_SYNC_RATE — check rate parameters to match against the rate_table parameters and adjust them if necessary.
• ROCKCHIP_PLL_FIXED_MODE — the pll operates in normal mode only.

bestie, these are the literal flag meanings — don't let the cute vibe make you miss them 💀

🦋 SEE ALSO 🦋

Kernel file ./drivers/clk/rockchip/clk.h struct rockchip_aux_grf(9), struct rockchip_clk_provider(9), struct rockchip_cpuclk_reg_data(9).

and that's the page, bestie 🫶 source/version ./drivers/clk/rockchip, dated October 2026, and it's all about struct rockchip_pll_clock(9). mwah 💋