STRUCT ROCKCHIP_PCIE_EP(9)

✨ struct rockchip_pcie_ep(9) ✨

okay so bestie, welcome to the Kernel API Manual 💅 this page is all about struct rockchip_pcie_ep and honestly? it's giving backstage-pass energy. it's the little private-data dressing room where the PCIe endpoint controller driver keeps all its stuff. no cap.

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🎀 NAME 🎀

struct rockchip_pcie_ep — private data for the PCIe endpoint controller driver 🦋

like, it's not the controller itself, it's the vibe of the controller. the personal stash. the group chat of variables. periodt.

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✨ SYNOPSIS ✨

struct rockchip_pcie_ep {
    struct rockchip_pcie    rockchip;
    struct pci_epc          *epc;
    u32 max_regions;
    unsigned long           ob_region_map;
    phys_addr_t *ob_addr;
    phys_addr_t irq_phys_addr;
    void __iomem            *irq_cpu_addr;
    u64 irq_pci_addr;
    u8 irq_pci_fn;
    u8 irq_pending;
    int perst_irq;
    bool perst_asserted;
    bool link_up;
    struct delayed_work     link_training;
 };

look at her. fourteen fields. main character struct honestly 🌸 copy it exactly if you're writing it out, bestie — no freelancing, no renaming, we do not do that here 🫶

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💖 Members 💖

the roster, one by one 👑

• rockchip — the Rockchip PCIe controller itself. the parent figure. the whole reason we're here 💜
• epc — the PCI EPC device. pointer city.
• max_regions — the maximum number of regions the hardware can support. like the seat limit at a concert — the hardware decides it, not you 🎫
• ob_region_map — a bitmask of the mapped outbound regions. yes, a <highlight>bitmask</highlight>, so if you're squinting at hex wondering which regions are live, this is your girl 🔥
• ob_addr — base addresses in the AXI bus where the outbound regions start. AXI bus addresses, not vibes-based addresses 💀
• irq_phys_addr — the base address on the AXI bus where the MSI/INTX IRQ dedicated outbound region is mapped. that's the physical side of the dedicated region, iykyk.
• irq_cpu_addr — the base address in CPU space where a write access triggers the sending of a memory write (MSI) / normal message (INTX IRQ) TLP through the PCIe bus. so like... you poke this address in CPU space, and a TLP goes out over PCIe. cute little trigger finger 🎀
• irq_pci_addr — used to save the current mapping of the MSI/INTX IRQ dedicated outbound region. it's the saved-state flex 💅
• irq_pci_fn — the latest PCI function that has updated the mapping of the MSI/INTX IRQ dedicated outbound region. i.e. who touched the mapping last. we keep receipts 🙈
• irq_pending — a bitmask of asserted INTX IRQs. again: <highlight>bitmask</highlight>. multiple bits, multiple asserted IRQs, one field.
• perst_irq — the IRQ used for the PERST# signal. (yes, with the hash. it's that signal ✨)
• perst_asserted — true if the PERST# signal was asserted. that's it, that's the whole field 🌈
• link_up — true if the PCI link is up. genuinely iconic. the field we all care about 😭
• link_training — the work item used to execute PCI link training. it's a struct delayed_work, so it laces up and does the training later. scheduled glow-up 🧚

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🌸 SEE ALSO 🌸

• Kernel file ./drivers/pci/controller/pcie-rockchip-ep.c — go read the source, bestie, it's right there and it ate 💖

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ngl, the whole point of this struct is that the driver keeps its state together in one place instead of scattering it, so if you're reading the driver and see a rockchip_pcie_ep pointer, that's the stash. you're welcome 🫶

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and that's the whole page!! slay 🌈⭐ this gorgeous little writeup comes to you from ./drivers/pci/controller, dated October 2026 — mwah, go touch the source, ily bye 💋🎀