STRUCT RISCV_IOMMU_PQ_RECORD(9)

💖 struct riscv_iommu_pq_record(9) 💖

okay so bestie, welcome to the Kernel API Manual entry for struct riscv_iommu_pq_record(9) — yes the title got squished in the header but we're folding it in here because we're polite like that ✨

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🌸 NAME 🌸

struct riscv_iommu_pq_record — the PCIe Page Request record, and honestly? she's iconic for it 💅

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🦋 SYNOPSIS 🦋

struct riscv_iommu_pq_record {
    u64 hdr;
    u64 payload;
};

two u64s. that's it. that's the whole girl. minimal, clean, main character energy 👑

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🎀 Members 🎀

• hdr — the header, and it's giving "I contain PID, DID etc" — like yes she holds the IDs, we love a record with range 💖
• payload — miss payload is carrying the page address, the request group, AND the permission bits. a whole triple threat. we stan 🫶

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✨ Description ✨

so if you want the actual lore on the PCIe Page Request queue, the manpage says to check chapter 3.3. that's the assignment, bestie. go read chapter 3.3 🔥

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🌈 SEE ALSO 🌈

• Kernel file ./drivers/iommu/riscv/iommu-bits.h enum
• riscv_iommu_igs_settings(9)
• enum riscv_iommu_ddtp_modes(9)
• enum riscv_iommu_hpmevent_id(9)
• struct riscv_iommu_dc(9)
• enum riscv_iommu_dc_iohgatp_modes(9)
• enum riscv_iommu_dc_fsc_atp_modes(9)
• struct riscv_iommu_pc(9)
• struct riscv_iommu_command(9)
• struct riscv_iommu_fq_record(9)
• enum riscv_iommu_fq_causes(9)
• enum riscv_iommu_fq_ttypes(9)
• struct riscv_iommu_msipte(9)

like, the whole riscv iommu friend group showed up. no cap, that's a full squad 🧚💜

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and that's the whole page, bestie!! 🎀 source is ./drivers/iommu/riscv, dated October 2026, and the poor header/footer got mangled into struct riscv...mu_pq_record(9) which is lowkey tragic but SO funny 😭 anyway ily, go read your structs 💖🌸🦋