STRUCT RISCV_IOMMU_MSIPTE(9)

✨ struct riscv_iommu_msipte(9) ✨

okay so bestie, welcome to the Kernel API Manual 💖 this one's a little struct page, and it's honestly giving "small but crucial" energy. let's get into it 🎀

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🌸 NAME 🌸

struct riscv_iommu_msipte — literally the MSI Page Table Entry. that's the whole vibe. ✨

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🦋 SYNOPSIS 🦋

here's the whole thing, and yes it's only two fields, she's compact and she knows it 💅

struct riscv_iommu_msipte {
    u64 pte;
    u64 mrif_info;
 };

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🎀 MEMBERS 🎀

• pte — the MSI PTE itself. the main character of the struct ngl 👑
• mrif_info — the memory-resident interrupt file info. think of it as the little side-pocket field 🫶

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💜 DESCRIPTION 💜

so the MSI Page Table is what you use to virtualize MSIs ✨ and the way that works is: when a device fires off an MSI at a guest, the IOMMU can reroute it by translating the MSI address — and it can send it either to a guest interrupt file or to a memory resident interrupt file (MRIF). either way, she's rehoming that interrupt, no cap 💅

⚠️ important detail bestie: this page table is an array of MSI PTEs, not a multi-level pt. every single entry is a leaf entry. so don't go looking for levels, there are none 🙈

for more infos (yes, for more infos, that's the lore 😭) check out the AIA spec, chapter 9.5. that's where the real reading happens 📖

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🌈 the basic mode situation 🌈

okay so in basic mode, the IOMMU straight up ignores the mrif_info field — so it's free real estate for software to use however it wants 🎉 lowkey the best kind of field.

💀 but here's the caveat and it's fr fr serious: any other reserved fields on pte must be zeroed-out by software. not optional, not a vibe check you can skip. zero them out. 💅

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⭐ SEE ALSO ⭐

• Kernel file ./drivers/iommu/riscv/iommu-bits.h enum
• riscv_iommu_igs_settings(9)
• enum riscv_iommu_ddtp_modes(9)
• enum riscv_iommu_hpmevent_id(9)
• struct riscv_iommu_dc(9)
• enum riscv_iommu_dc_iohgatp_modes(9)
• enum riscv_iommu_dc_fsc_atp_modes(9)
• struct riscv_iommu_pc(9)
• struct riscv_iommu_command(9)
• struct riscv_iommu_fq_record(9)
• enum riscv_iommu_fq_causes(9)
• enum riscv_iommu_fq_ttypes(9)
• struct riscv_iommu_pq_record(9)

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and that's the page!! 🦋 go read chapter 9.5 of the AIA spec and remember to zero your reserved bits, i'm literally begging 🙏

signed off with love from ./drivers/iommu/riscv, dated October 2026 — catch you in the next struct, bestie 💖✨🎀