STRUCT REGMAP_CONFIG(9)
π struct regmap_config(9) β Kernel API Manual π
okay so the manual name on this one is struct regmap_config(9) β¨ and honestly the number in the parens is doing a lot of heavy lifting because this page is long. Like, so long that we're splitting it into two parts β this is part 1, and it's the "here's the whole struct, take it in, let it wash over you" part. We are not skipping a single line. Not one. Periodt. π
β¨ NAME β¨
struct regmap_config β the configuration for the register map of a device π
That's the whole name section. Minimalist. Iconic. It's giving "the struct IS the personality."
π¦ SYNOPSIS π¦
okay bestie, deep breath, here's the whole thing in one shot, exactly as written:
struct regmap_config {
const char *name;
int reg_bits;
int reg_stride;
int reg_shift;
unsigned int reg_base;
int pad_bits;
int val_bits;
bool (*writeable_reg)(struct device *dev, unsigned int reg);
bool (*readable_reg)(struct device *dev, unsigned int reg);
bool (*volatile_reg)(struct device *dev, unsigned int reg);
bool (*precious_reg)(struct device *dev, unsigned int reg);
bool (*writeable_noinc_reg)(struct device *dev, unsigned int reg);
bool (*readable_noinc_reg)(struct device *dev, unsigned int reg);
int (*reg_read)(void *context, unsigned int reg, unsigned int *val);
int (*reg_write)(void *context, unsigned int reg, unsigned int val);
int (*reg_update_bits)(void *context, unsigned int reg, unsigned int
mask, unsigned int val);
int (*read)(void *context, const void *reg_buf, size_t reg_size,
void *val_buf, size_t val_size);
int (*write)(void *context, const void *data, size_t count);
size_t max_raw_read;
size_t max_raw_write;
bool can_sleep;
bool fast_io;
bool io_port;
bool disable_locking;
regmap_lock lock;
regmap_unlock unlock;
void *lock_arg;
unsigned int max_register;
bool max_register_is_0;
const struct regmap_access_table *wr_table;
const struct regmap_access_table *rd_table;
const struct regmap_access_table *volatile_table;
const struct regmap_access_table *precious_table;
const struct regmap_access_table *wr_noinc_table;
const struct regmap_access_table *rd_noinc_table;
const struct reg_default *reg_defaults;
unsigned int num_reg_defaults;
int (*reg_default_cb)(struct device *dev, unsigned int reg, unsigned
int *def);
enum regcache_type cache_type;
const void *reg_defaults_raw;
unsigned int num_reg_defaults_raw;
unsigned long read_flag_mask;
unsigned long write_flag_mask;
bool zero_flag_mask;
bool use_single_read;
bool use_single_write;
bool use_relaxed_mmio;
bool can_multi_write;
bool use_hwlock;
bool use_raw_spinlock;
unsigned int hwlock_id;
unsigned int hwlock_mode;
enum regmap_endian reg_format_endian;
enum regmap_endian val_format_endian;
const struct regmap_range_cfg *ranges;
unsigned int num_ranges;
};
πΈ a lil tour of the vibes πΈ
so like, the shape of this thing is genuinely so satisfying to look at, let me walk you through it the way I'd show you a really good outfit:
- π«Ά it opens with a tiny cluster of numbers about regs and vals β
name, thenreg_bits,reg_stride,reg_shift,reg_base,pad_bits,val_bits. (yes,reg_baseis anunsigned intwhile its neighbours are plainint, we don't make the rules π ) - β¨ then comes the callback squad:
writeable_reg,readable_reg,volatile_reg,precious_reg,writeable_noinc_reg,readable_noinc_regβ sixboolfunction pointers, all taking(struct device *dev, unsigned int reg). matching outfits. love that for them. - π₯ then the I/O trio:
reg_read,reg_write,reg_update_bitsβ allint-returning, all takingvoid *context.reg_update_bitsbrings along amaskand avalfor the ride. - π then the raw pair,
readandwrite, hanging out withsize_t max_raw_readandsize_t max_raw_write. - π then a stack of
bools:can_sleep,fast_io,io_port,disable_locking. four in a row. slay. - π then the lock little family β
regmap_lock lock,regmap_unlock unlock,void *lock_arg. - π then
unsigned int max_registerandbool max_register_is_0, followed by all six access tables:wr_table,rd_table,volatile_table,precious_table,wr_noinc_table,rd_noinc_tableβ every one of them aconst struct regmap_access_table *. - π then the defaults block:
reg_defaults,num_reg_defaults, thereg_default_cbfunction pointer,enum regcache_type cache_type,reg_defaults_raw,num_reg_defaults_raw. - π§ then masks and more
bools:read_flag_mask,write_flag_mask,zero_flag_mask,use_single_read,use_single_write,use_relaxed_mmio,can_multi_write,use_hwlock,use_raw_spinlock,hwlock_id,hwlock_mode. - β and it closes with
reg_format_endianandval_format_endian(bothenum regmap_endian), thenrangesandnum_ranges, and finally that one little};sitting at the end with a single extra space in front of it. character.
ngl this is a lot of fields and we have not even gotten to the part where it explains what any of them do β that's part 2, bestie. hydrate first. π«Ά
okay that's the shape of it β do NOT close the tab, the lore is literally loading π
π MEMBERS π
okay bestie, this is the big one β every single field in struct regmap_config, in order, no skips. grab a snack π
nameβ optional name of the regmap. super useful when one device has multiple register regions and you need to tell them apart. iykyk π·οΈreg_bitsβ number of bits in a register address. mandatory, no cap, you literally cannot skip this one πreg_strideβ the register address stride. valid register addresses are a multiple of this value. and if you set it to0, a value of1will be used. she's got a fallback β¨reg_shiftβ the number of bits to shift the register before performing any operations. any positive number will be downshifted, and negative values will be upshifted. direction girlies πΈreg_baseβ value to be added to every register address before performing any operation. tiny little offset, big main character energy πpad_bitsβ number of bits of padding between register and value. the filler bits, we respect them πval_bitsβ number of bits in a register value. also mandatory. yes both. periodt πwriteable_regβ optional callback returningtrueif the register can be written to. if this field isNULLbutwr_table(see below) is not, the check is performed on such table (a register is writeable if it belongs to one of the ranges specified bywr_table). callback or table, pick your fighter π«Άreadable_regβ optional callback returningtrueif the register can be read from. if this field isNULLbutrd_table(see below) is not, the check is performed on such table (a register is readable if it belongs to one of the ranges specified byrd_table). same deal, same slay β¨volatile_regβ optional callback returningtrueif the register value can't be cached. if this field isNULLbutvolatile_table(see below) is not, the check is performed on such table (a register is volatile if it belongs to one of the ranges specified byvolatile_table). no caching for these divas π₯precious_regβ optional callback returningtrueif the register should not be read outside of a call from the driver (e.g. a clear on read interrupt status register). if this field isNULLbutprecious_table(see below) is not, the check is performed on such table (a register is precious if it belongs to one of the ranges specified byprecious_table). yes she's literally called precious, she's earned it πwriteable_noinc_regβ optional callback returningtrueif the register supports multiple write operations without incrementing the register number. if this field isNULLbutwr_noinc_table(see below) is not, the check is performed on such table (a register is no increment writeable if it belongs to one of the ranges specified bywr_noinc_table). same address, over and over, iconic πreadable_noinc_regβ optional callback returningtrueif the register supports multiple read operations without incrementing the register number. if this field isNULLbutrd_noinc_table(see below) is not, the check is performed on such table (a register is no increment readable if it belongs to one of the ranges specified byrd_noinc_table). matching set, read edition πreg_readβ optional callback that, if filled, will be used to perform all the reads from the registers. should only be provided for devices whose read operation cannot be represented as a simple read operation on a bus such asSPI,I2C, etc. most of the devices do not need this. ngl if you're reaching for this one, you know who you are πreg_writeβ same as above, but for writing. βοΈreg_update_bitsβ optional callback that, if filled, will be used to perform all theupdate_bits(rmw)operation. should only be provided if the function require special handling with lock and reg handling and the operation cannot be represented as a simpleupdate_bitsoperation on a bus such asSPI,I2C, etc. read-modify-write girlies rise πreadβ optional callback that, if filled, will be used to perform all the bulk reads from the registers. data is returned in the buffer used to transmit data. yes, the same buffer. the way that works is very much a vibe π«Άwriteβ same as above, for writing. π«max_raw_readβ max raw read size that can be used on the device. πmax_raw_writeβ max raw write size that can be used on the device. πcan_sleepβ optional, specifies whether regmap operations can sleep. sleepy girl rights π΄fast_ioβ register IO is fast. use aspinlockinstead of amutexto perform locking. this field is ignored if custom lock/unlock functions are used (see fieldslock/unlockofstruct regmap_config). this field is a duplicate of a similar file in β okay the manpage literally trails off there, bestie, i'm not making that up π β use it only for "no-bus" cases. β‘io_portβ support IO port accessors. makes sense only when MMIO vs. IO port access can be distinguished. πͺdisable_lockingβ this regmap is either protected by external means or is guaranteed not to be accessed from multiple threads. don't use any locking mechanisms. bold move, we love a confident driver πlockβ optional lock callback (overrides regmap's default lock function, based onspinlockormutex). πunlockβ as above, for unlocking. πlock_argβ this field is passed as the only argument oflock/unlockfunctions (ignored in case regularlock/unlockfunctions are not overridden). one arg, no notes πmax_registerβ optional, specifies the maximum valid register address. πmax_register_is_0β optional, specifies that a zero value inmax_registershould be taken into account. this is a workaround to apply handling ofmax_registerfor regmap that contains only one register. one single register and she still needs a whole flag πwr_tableβ optional, points to astruct regmap_access_tablespecifying valid ranges for write access. πrd_tableβ as above, for read access. πvolatile_tableβ as above, for volatile registers. πprecious_tableβ as above, for precious registers. πwr_noinc_tableβ as above, for no increment writeable registers. πrd_noinc_tableβ as above, for no increment readable registers. πreg_defaultsβ power on reset values for registers (for use with register cache support). πnum_reg_defaultsβ number of elements inreg_defaults. π’reg_default_cbβ optional callback to return default values for registers not listed inreg_defaults. this is only used forREGCACHE_FLATpopulation; drivers must ensure thereadable_reg/writeable_regcallbacks are defined to handle holes. yes, holes. handle them π³οΈcache_typeβ the actual cache type. just one line, she's mysterious like that πreg_defaults_rawβ power on reset values for registers (for use with register cache support). the raw version, the unformatted one πnum_reg_defaults_rawβ number of elements inreg_defaults_raw. π’read_flag_maskβ mask to be set in the top bytes of the register when doing a read. πwrite_flag_maskβ mask to be set in the top bytes of the register when doing a write. if bothread_flag_maskandwrite_flag_maskare empty andzero_flag_maskis not set, theregmap_busdefault masks are used. so like, they've got a fallback, but only sometimes π€zero_flag_maskβ if set,read_flag_maskandwrite_flag_maskare used even if they are both empty. this is the "yes i meant empty" flag π«‘use_single_readβ if set, converts the bulk read operation into a series of single read operations. useful for a device that does not support bulk read. one at a time, bestie πuse_single_writeβ if set, converts the bulk write operation into a series of single write operations. useful for a device that does not support bulk write. same energy, write edition π’use_relaxed_mmioβ if set, MMIO R/W operations will not use memory barriers. this can avoid load on devices which don't require strict orderings, but drivers should carefully add any explicit memory barriers when they may require them. > bestie listen to me: relaxed means relaxed, and if you needed those barriers you're on your own to add them. be careful, fr fr β οΈcan_multi_writeβ if set, the device supports the multi write mode of bulk write operations; if clear, multi write requests will be split into individual write operations. she's either all in or one by one β¨use_hwlockβ indicate if a hardware spinlock should be used. π§²use_raw_spinlockβ indicate if a raw spinlock should be used. πhwlock_idβ specify the hardware spinlock id. πhwlock_modeβ the hardware spinlock mode, should beHWLOCK_IRQSTATE,HWLOCK_IRQor0. them's the options π β and note "should be", so like, don't get creative.reg_format_endianβ endianness for formatted register addresses. if this isDEFAULT, thereg_format_endian_defaultvalue from the regmap bus is used. π«val_format_endianβ endianness for formatted register values. if this isDEFAULT, thereg_format_endian_defaultvalue from the regmap bus is used. (yes, same wording as the line above β i'm just the messenger π«Ά)rangesβ array of configuration entries for virtual address ranges. πΊοΈnum_rangesβ number of range configuration entries. π’
β¨ SEE ALSO β¨
okay so the gang's all here, kernel file ./include/linux/regmap.h, and then this whole friend group:
struct reg_default(9)struct reg_sequence(9)regmap_read_poll_timeout(9)regmap_read_poll_timeout_atomic(9)regmap_field_read_poll_timeout(9)struct regmap_range(9)struct regmap_access_table(9)struct regmap_range_cfg(9)struct regmap_sdw_mbq_cfg(9)struct regmap_bus(9)regmap_init(9)regmap_init_i2c(9)regmap_init_mdio(9)regmap_init_sccb(9)regmap_init_slimbus(9)regmap_init_spi(9)regmap_init_spmi_base(9)regmap_init_spmi_ext(9)regmap_init_w1(9)regmap_init_mmio_clk(9)regmap_init_mmio(9)regmap_init_ac97(9)regmap_init_sdw(9)regmap_init_sdw_mbq(9)regmap_init_sdw_mbq_cfg(9)regmap_init_i3c(9)regmap_init_spi_avmm(9)regmap_init_fsi(9)devm_regmap_init(9)devm_regmap_init_i2c(9)devm_regmap_init_mdio(9)devm_regmap_init_sccb(9)devm_regmap_init_spi(9)devm_regmap_init_spmi_base(9)devm_regmap_init_spmi_ext(9)devm_regmap_init_w1(9)devm_regmap_init_mmio_clk(9)devm_regmap_init_mmio(9)devm_regmap_init_ac97(9)devm_regmap_init_sdw(9)devm_regmap_init_sdw_mbq(9)devm_regmap_init_sdw_mbq_cfg(9)devm_regmap_init_slimbus(9)devm_regmap_init_i3c(9)devm_regmap_init_spi_avmm(9)devm_regmap_init_fsi(9)struct reg_field(9)struct regmap_irq_type(9)struct regmap_irq(9)struct regmap_irq_chip(9)
and that's the whole page, bestie, you made it π«Ά this one came from the kernel source tree at ./include/linux, dated October 2026, and it's all about struct regmap_config(9) β go forth and configure your registers, i'm obsessed with you πβ¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms