STRUCT REGMAP_CONFIG(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– struct regmap_config(9) β€” Kernel API Manual πŸ’–

okay so the manual name on this one is struct regmap_config(9) ✨ and honestly the number in the parens is doing a lot of heavy lifting because this page is long. Like, so long that we're splitting it into two parts β€” this is part 1, and it's the "here's the whole struct, take it in, let it wash over you" part. We are not skipping a single line. Not one. Periodt. πŸ’…


✨ NAME ✨

struct regmap_config β€” the configuration for the register map of a device πŸŽ€

That's the whole name section. Minimalist. Iconic. It's giving "the struct IS the personality."


πŸ¦‹ SYNOPSIS πŸ¦‹

okay bestie, deep breath, here's the whole thing in one shot, exactly as written:

struct regmap_config {
    const char *name;
    int reg_bits;
    int reg_stride;
    int reg_shift;
    unsigned int reg_base;
    int pad_bits;
    int val_bits;
    bool (*writeable_reg)(struct device *dev, unsigned int reg);
    bool (*readable_reg)(struct device *dev, unsigned int reg);
    bool (*volatile_reg)(struct device *dev, unsigned int reg);
    bool (*precious_reg)(struct device *dev, unsigned int reg);
    bool (*writeable_noinc_reg)(struct device *dev, unsigned int reg);
    bool (*readable_noinc_reg)(struct device *dev, unsigned int reg);
    int (*reg_read)(void *context, unsigned int reg, unsigned int *val);
    int (*reg_write)(void *context, unsigned int reg, unsigned int val);
    int (*reg_update_bits)(void *context, unsigned int reg, unsigned int
mask, unsigned int val);
    int (*read)(void *context, const void *reg_buf, size_t reg_size,
void *val_buf, size_t val_size);
    int (*write)(void *context, const void *data, size_t count);
    size_t max_raw_read;
    size_t max_raw_write;
    bool can_sleep;
    bool fast_io;
    bool io_port;
    bool disable_locking;
    regmap_lock lock;
    regmap_unlock unlock;
    void *lock_arg;
    unsigned int max_register;
    bool max_register_is_0;
    const struct regmap_access_table *wr_table;
    const struct regmap_access_table *rd_table;
    const struct regmap_access_table *volatile_table;
    const struct regmap_access_table *precious_table;
    const struct regmap_access_table *wr_noinc_table;
    const struct regmap_access_table *rd_noinc_table;
    const struct reg_default *reg_defaults;
    unsigned int num_reg_defaults;
    int (*reg_default_cb)(struct device *dev, unsigned int reg, unsigned
int *def);
    enum regcache_type cache_type;
    const void *reg_defaults_raw;
    unsigned int num_reg_defaults_raw;
    unsigned long read_flag_mask;
    unsigned long write_flag_mask;
    bool zero_flag_mask;
    bool use_single_read;
    bool use_single_write;
    bool use_relaxed_mmio;
    bool can_multi_write;
    bool use_hwlock;
    bool use_raw_spinlock;
    unsigned int hwlock_id;
    unsigned int hwlock_mode;
    enum regmap_endian reg_format_endian;
    enum regmap_endian val_format_endian;
    const struct regmap_range_cfg *ranges;
    unsigned int num_ranges;
 };

🌸 a lil tour of the vibes 🌸

so like, the shape of this thing is genuinely so satisfying to look at, let me walk you through it the way I'd show you a really good outfit:

  • 🫢 it opens with a tiny cluster of numbers about regs and vals β€” name, then reg_bits, reg_stride, reg_shift, reg_base, pad_bits, val_bits. (yes, reg_base is an unsigned int while its neighbours are plain int, we don't make the rules πŸ’…)
  • ✨ then comes the callback squad: writeable_reg, readable_reg, volatile_reg, precious_reg, writeable_noinc_reg, readable_noinc_reg β€” six bool function pointers, all taking (struct device *dev, unsigned int reg). matching outfits. love that for them.
  • πŸ”₯ then the I/O trio: reg_read, reg_write, reg_update_bits β€” all int-returning, all taking void *context. reg_update_bits brings along a mask and a val for the ride.
  • 🌈 then the raw pair, read and write, hanging out with size_t max_raw_read and size_t max_raw_write.
  • πŸ’€ then a stack of bools: can_sleep, fast_io, io_port, disable_locking. four in a row. slay.
  • πŸŽ€ then the lock little family β€” regmap_lock lock, regmap_unlock unlock, void *lock_arg.
  • πŸ‘‘ then unsigned int max_register and bool max_register_is_0, followed by all six access tables: wr_table, rd_table, volatile_table, precious_table, wr_noinc_table, rd_noinc_table β€” every one of them a const struct regmap_access_table *.
  • πŸ“ then the defaults block: reg_defaults, num_reg_defaults, the reg_default_cb function pointer, enum regcache_type cache_type, reg_defaults_raw, num_reg_defaults_raw.
  • 🧚 then masks and more bools: read_flag_mask, write_flag_mask, zero_flag_mask, use_single_read, use_single_write, use_relaxed_mmio, can_multi_write, use_hwlock, use_raw_spinlock, hwlock_id, hwlock_mode.
  • ⭐ and it closes with reg_format_endian and val_format_endian (both enum regmap_endian), then ranges and num_ranges, and finally that one little }; sitting at the end with a single extra space in front of it. character.
ngl this is a lot of fields and we have not even gotten to the part where it explains what any of them do β€” that's part 2, bestie. hydrate first. 🫢

okay that's the shape of it β€” do NOT close the tab, the lore is literally loading πŸ’œ

πŸ’– MEMBERS πŸ’–

okay bestie, this is the big one β€” every single field in struct regmap_config, in order, no skips. grab a snack πŸ“

  • name β€” optional name of the regmap. super useful when one device has multiple register regions and you need to tell them apart. iykyk 🏷️
  • reg_bits β€” number of bits in a register address. mandatory, no cap, you literally cannot skip this one πŸ’…
  • reg_stride β€” the register address stride. valid register addresses are a multiple of this value. and if you set it to 0, a value of 1 will be used. she's got a fallback ✨
  • reg_shift β€” the number of bits to shift the register before performing any operations. any positive number will be downshifted, and negative values will be upshifted. direction girlies 🌸
  • reg_base β€” value to be added to every register address before performing any operation. tiny little offset, big main character energy πŸ‘‘
  • pad_bits β€” number of bits of padding between register and value. the filler bits, we respect them πŸŽ€
  • val_bits β€” number of bits in a register value. also mandatory. yes both. periodt πŸ’€
  • writeable_reg β€” optional callback returning true if the register can be written to. if this field is NULL but wr_table (see below) is not, the check is performed on such table (a register is writeable if it belongs to one of the ranges specified by wr_table). callback or table, pick your fighter 🫢
  • readable_reg β€” optional callback returning true if the register can be read from. if this field is NULL but rd_table (see below) is not, the check is performed on such table (a register is readable if it belongs to one of the ranges specified by rd_table). same deal, same slay ✨
  • volatile_reg β€” optional callback returning true if the register value can't be cached. if this field is NULL but volatile_table (see below) is not, the check is performed on such table (a register is volatile if it belongs to one of the ranges specified by volatile_table). no caching for these divas πŸ”₯
  • precious_reg β€” optional callback returning true if the register should not be read outside of a call from the driver (e.g. a clear on read interrupt status register). if this field is NULL but precious_table (see below) is not, the check is performed on such table (a register is precious if it belongs to one of the ranges specified by precious_table). yes she's literally called precious, she's earned it πŸ’…
  • writeable_noinc_reg β€” optional callback returning true if the register supports multiple write operations without incrementing the register number. if this field is NULL but wr_noinc_table (see below) is not, the check is performed on such table (a register is no increment writeable if it belongs to one of the ranges specified by wr_noinc_table). same address, over and over, iconic πŸŒ€
  • readable_noinc_reg β€” optional callback returning true if the register supports multiple read operations without incrementing the register number. if this field is NULL but rd_noinc_table (see below) is not, the check is performed on such table (a register is no increment readable if it belongs to one of the ranges specified by rd_noinc_table). matching set, read edition πŸŽ€
  • reg_read β€” optional callback that, if filled, will be used to perform all the reads from the registers. should only be provided for devices whose read operation cannot be represented as a simple read operation on a bus such as SPI, I2C, etc. most of the devices do not need this. ngl if you're reaching for this one, you know who you are 😭
  • reg_write β€” same as above, but for writing. ✍️
  • reg_update_bits β€” optional callback that, if filled, will be used to perform all the update_bits(rmw) operation. should only be provided if the function require special handling with lock and reg handling and the operation cannot be represented as a simple update_bits operation on a bus such as SPI, I2C, etc. read-modify-write girlies rise 🌈
  • read β€” optional callback that, if filled, will be used to perform all the bulk reads from the registers. data is returned in the buffer used to transmit data. yes, the same buffer. the way that works is very much a vibe 🫢
  • write β€” same as above, for writing. πŸ’«
  • max_raw_read β€” max raw read size that can be used on the device. πŸ“
  • max_raw_write β€” max raw write size that can be used on the device. πŸ“
  • can_sleep β€” optional, specifies whether regmap operations can sleep. sleepy girl rights 😴
  • fast_io β€” register IO is fast. use a spinlock instead of a mutex to perform locking. this field is ignored if custom lock/unlock functions are used (see fields lock/unlock of struct regmap_config). this field is a duplicate of a similar file in β€” okay the manpage literally trails off there, bestie, i'm not making that up πŸ™ˆ β€” use it only for "no-bus" cases. ⚑
  • io_port β€” support IO port accessors. makes sense only when MMIO vs. IO port access can be distinguished. πŸšͺ
  • disable_locking β€” this regmap is either protected by external means or is guaranteed not to be accessed from multiple threads. don't use any locking mechanisms. bold move, we love a confident driver πŸ’€
  • lock β€” optional lock callback (overrides regmap's default lock function, based on spinlock or mutex). πŸ”’
  • unlock β€” as above, for unlocking. πŸ”“
  • lock_arg β€” this field is passed as the only argument of lock/unlock functions (ignored in case regular lock/unlock functions are not overridden). one arg, no notes 🎁
  • max_register β€” optional, specifies the maximum valid register address. 🏁
  • max_register_is_0 β€” optional, specifies that a zero value in max_register should be taken into account. this is a workaround to apply handling of max_register for regmap that contains only one register. one single register and she still needs a whole flag 😭
  • wr_table β€” optional, points to a struct regmap_access_table specifying valid ranges for write access. πŸ“‹
  • rd_table β€” as above, for read access. πŸ“‹
  • volatile_table β€” as above, for volatile registers. πŸ“‹
  • precious_table β€” as above, for precious registers. πŸ“‹
  • wr_noinc_table β€” as above, for no increment writeable registers. πŸ“‹
  • rd_noinc_table β€” as above, for no increment readable registers. πŸ“‹
  • reg_defaults β€” power on reset values for registers (for use with register cache support). πŸ”Œ
  • num_reg_defaults β€” number of elements in reg_defaults. πŸ”’
  • reg_default_cb β€” optional callback to return default values for registers not listed in reg_defaults. this is only used for REGCACHE_FLAT population; drivers must ensure the readable_reg/writeable_reg callbacks are defined to handle holes. yes, holes. handle them πŸ•³οΈ
  • cache_type β€” the actual cache type. just one line, she's mysterious like that πŸ’…
  • reg_defaults_raw β€” power on reset values for registers (for use with register cache support). the raw version, the unformatted one 🌈
  • num_reg_defaults_raw β€” number of elements in reg_defaults_raw. πŸ”’
  • read_flag_mask β€” mask to be set in the top bytes of the register when doing a read. 🎭
  • write_flag_mask β€” mask to be set in the top bytes of the register when doing a write. if both read_flag_mask and write_flag_mask are empty and zero_flag_mask is not set, the regmap_bus default masks are used. so like, they've got a fallback, but only sometimes 😀
  • zero_flag_mask β€” if set, read_flag_mask and write_flag_mask are used even if they are both empty. this is the "yes i meant empty" flag 🫑
  • use_single_read β€” if set, converts the bulk read operation into a series of single read operations. useful for a device that does not support bulk read. one at a time, bestie 🐌
  • use_single_write β€” if set, converts the bulk write operation into a series of single write operations. useful for a device that does not support bulk write. same energy, write edition 🐒
  • use_relaxed_mmio β€” if set, MMIO R/W operations will not use memory barriers. this can avoid load on devices which don't require strict orderings, but drivers should carefully add any explicit memory barriers when they may require them. > bestie listen to me: relaxed means relaxed, and if you needed those barriers you're on your own to add them. be careful, fr fr ⚠️
  • can_multi_write β€” if set, the device supports the multi write mode of bulk write operations; if clear, multi write requests will be split into individual write operations. she's either all in or one by one ✨
  • use_hwlock β€” indicate if a hardware spinlock should be used. 🧲
  • use_raw_spinlock β€” indicate if a raw spinlock should be used. πŸŒ€
  • hwlock_id β€” specify the hardware spinlock id. πŸ†”
  • hwlock_mode β€” the hardware spinlock mode, should be HWLOCK_IRQSTATE, HWLOCK_IRQ or 0. them's the options πŸ‘‘ β€” and note "should be", so like, don't get creative.
  • reg_format_endian β€” endianness for formatted register addresses. if this is DEFAULT, the reg_format_endian_default value from the regmap bus is used. πŸ’«
  • val_format_endian β€” endianness for formatted register values. if this is DEFAULT, the reg_format_endian_default value from the regmap bus is used. (yes, same wording as the line above β€” i'm just the messenger 🫢)
  • ranges β€” array of configuration entries for virtual address ranges. πŸ—ΊοΈ
  • num_ranges β€” number of range configuration entries. πŸ”’

✨ SEE ALSO ✨

okay so the gang's all here, kernel file ./include/linux/regmap.h, and then this whole friend group:


and that's the whole page, bestie, you made it 🫢 this one came from the kernel source tree at ./include/linux, dated October 2026, and it's all about struct regmap_config(9) β€” go forth and configure your registers, i'm obsessed with you πŸ’–βœ¨

πŸ“¦ where this page comes from