STRUCT PRIV1_CACHE(9)

🧚‍♀️ struct priv1_cache(9) — Kernel API Manual 🧚‍♀️

okay bestie, welcome to the Kernel API Manual 💖 today’s main character is struct priv1_cache, and she is literally giving “cached values of priv1 registers” energy. Also keep @masks[] in mind: Array of cached spe interrupt masks, indexed by class. no cap ✨

🌸 NAME 🌸

struct priv1_cache — Cached values of priv1 registers. @masks[]: Array of cached spe interrupt masks, indexed by class. 💅

✨ SYNOPSIS ✨

struct priv1_cache {
    u64 masks[3];
    u64 sr1;
    u64 tclass_id;
};

🎀 Members 🎀

• sr1 — Cached mfc_sr1 register. literally the mfc_sr1 cache, periodt 🦋
• tclass_id — Cached mfc_tclass_id register. yes bestie, mfc_tclass_id is cached too 💜

👑 SEE ALSO 👑

Kernel file ./arch/powerpc/platforms/ps3/spu.c plus these iconic little friends: enum spe_type(9), struct spe_shadow(9), enum spe_ex_state(9), struct spu_pdata(9), setup_areas(9), ps3_enable_spu(9). iykyk 🌈

mwah 💋 this page lives under ./arch/powerpc/platforms/ps3, is dated October 2026, and it’s all about struct priv1_cache(9). slay 🫶