STRUCT PMC_REG_MAP(9)

💖 NAME 💖

okay so bestie, this is struct pmc_reg_map from the Kernel API Manual, section 9, and the NAME line says: struct pmc_reg_map — Structure used to define parameter unique to a. yes, it really does stop at “a” — iconic cliffhanger energy, no cap 💅.

✨ SYNOPSIS ✨

here’s the whole struct lineup, character for character, because we respect the lore 🫶:

struct pmc_reg_map {
    const struct pmc_bit_map **pfear_sts;
    const struct pmc_bit_map *mphy_sts;
    const struct pmc_bit_map *pll_sts;
    const struct pmc_bit_map **slps0_dbg_maps;
    const struct pmc_bit_map *ltr_show_sts;
    const struct pmc_bit_map *msr_sts;
    const struct pmc_bit_map **lpm_sts;
    const struct pmc_bit_map **s0ix_blocker_maps;
    const u32 slp_s0_offset;
    const int slp_s0_res_counter_step;
    const u32 ltr_ignore_offset;
    const int regmap_length;
    const u32 ppfear0_offset;
    const int ppfear_buckets;
    const u32 pm_cfg_offset;
    const int pm_read_disable_bit;
    const u32 slps0_dbg_offset;
    const u32 ltr_ignore_max;
    const u32 pm_vric1_offset;
    const u32 s0ix_blocker_offset;
    const u32 num_s0ix_blocker;
    const u32 blocker_req_offset;
    const int lpm_num_maps;
    const int lpm_num_modes;
    const int lpm_res_counter_step_x2;
    const u32 lpm_sts_latch_en_offset;
    const u32 lpm_en_offset;
    const u32 lpm_priority_offset;
    const u32 lpm_residency_offset;
    const u32 lpm_status_offset;
    const u32 lpm_live_status_offset;
    const u32 etr3_offset;
    const u8  *lpm_reg_index;
    const u32 pson_residency_offset;
    const u32 pson_residency_counter_step;
    const u32 lpm_req_guid;
 };

🎀 Members 🎀

okay so this Members list is a lil selective — some fields are just vibing in the synopsis without their own blurb. here’s every member description the page actually gives, bestie 💖:

• pfear_sts — Maps name of IP block to PPFEAR* bit
• mphy_sts — Maps name of MPHY lane to MPHY status lane status bit
• pll_sts — Maps name of PLL to corresponding bit status
• slps0_dbg_maps — Array of SLP_S0_DBG* registers containing debug info
• ltr_show_sts — Maps PCH IP Names to their MMIO register offsets
• s0ix_blocker_maps — Maps name of IP block to S0ix blocker counter
• slp_s0_offset — PWRMBASE offset to read SLP_S0 residency
• ltr_ignore_offset — PWRMBASE offset to read/write LTR ignore bit
• regmap_length — Length of memory to map from PWRMBASE address to access
• ppfear0_offset — PWRMBASE offset to read PPFEAR*
• ppfear_buckets — Number of 8 bits blocks to read all IP blocks from PPFEAR
• pm_cfg_offset — PWRMBASE offset to PM_CFG register
• pm_read_disable_bit — Bit index to read PMC_READ_DISABLE
• slps0_dbg_offset — PWRMBASE offset to SLP_S0_DEBUG_REG* s0ix_blocker_offset — PWRMBASE offset to S0ix blocker counter
• num_s0ix_blocker — Number of S0ix blockers
• blocker_req_offset — Telemetry offset to S0ix blocker low power mode substate requirement table
• lpm_req_guid — Telemetry GUID to read low power mode substate requirement table

💖 Description 💖

Every PCH is out here with its own unique set of register offsets and bit indexes ✨ this structure captures all of that so there can be a common implementation — it’s giving shared-codebase main character energy, periodt 💅.

👑 SEE ALSO 👑

Kernel file ./drivers/platform/x86/intel/pmc/core.h, plus struct pmc_info(9), struct pmc(9), struct pmc_dev(9), and struct pmc_dev_info(9) — go read those next, bestie 📚🦋.

and that’s the tea ☕ this page is from ./drivers/platform/x86/intel/pmc, dated October 2026, and it’s literally titled struct pmc_reg_map(9) — bye bestie, go read some kernel code 💖🎀