STRUCT OWL_PINGROUP(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

🌈 struct owl_pingroup(9) 🌈

okay so this page is straight out of the Kernel API Manual, and it’s giving β€œtiny but crucial pinctrl struct” energy πŸ¦‹. We’re talking about struct owl_pingroup β€” the Actions pingroup definition β€” and yes, every member is getting its moment πŸ’….

✨ NAME ✨

struct owl_pingroup β€” Actions pingroup definition πŸ‘‘

πŸŽ€ SYNOPSIS πŸŽ€

       struct owl_pingroup {
           const char *name;
           unsigned int *pads;
           unsigned int npads;
           unsigned int *funcs;
           unsigned int nfuncs;
           int mfpctl_reg;
           unsigned int mfpctl_shift;
           unsigned int mfpctl_width;
           int drv_reg;
           unsigned int drv_shift;
           unsigned int drv_width;
           int sr_reg;
           unsigned int sr_shift;
           unsigned int sr_width;
        };

🌸 Members 🌸

okay bestie, here’s the member-by-member tour, no skipping, no β€œI’ll read it later” πŸ™ˆ:

  • name β€” name of the pin group. It’s the group’s little ID badge πŸ’–.
  • pads β€” list of pins assigned to this pingroup. Think guest list, but for pads ✨.
  • npads β€” size of pads array. So you know how many pins are on that list πŸŽ€.
  • funcs β€” list of pinmux functions for this pingroup. The function menu, basically πŸ“.
  • nfuncs β€” size of funcs array. The count for that function menu πŸ”’.
  • mfpctl_reg β€” multiplexing control register offset. Where the mux control register sits πŸ“.
  • mfpctl_shift β€” multiplexing control register bit mask. The mask situation inside that multiplexing control register 🎭.
  • mfpctl_width β€” multiplexing control register width. How wide that multiplexing control register situation is πŸ“.
  • drv_reg β€” drive control register offset. Drive control register location unlocked πŸš—.
  • drv_shift β€” drive control register bit mask. The bit mask for the drive control register 🎚️.
  • drv_width β€” driver control register width. Width of the driver control register, exactly as stated πŸ‘‘.
  • sr_reg β€” slew rate control register offset. Slew rate control register, found at this offset 🌈.
  • sr_shift β€” slew rate control register bit mask. Bit mask for the slew rate control register 🧚.
  • sr_width β€” slew rate control register width. Width of the slew rate control register ⭐.

πŸ”₯ SEE ALSO πŸ”₯

Kernel file ./drivers/pinctrl/actions/pinctrl-owl.h is the source-file main character here, and it says go look at these too:

  • struct owl_pullctl(9)
  • struct owl_st(9)
  • struct owl_padinfo(9)
  • struct owl_pinmux_func(9)
  • struct owl_gpio_port(9)
  • struct owl_pinctrl_soc_data(9)

that’s the whole page, bestie πŸ’œ β€” source spot: ./drivers/pinctrl/actions Β· date: October 2026 Β· page: struct owl_pingroup(9). slay and read the struct 🫢.

πŸ“¦ where this page comes from