STRUCT OMAP_PRCM_IRQ(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… NAME πŸ’…

ok so struct omap_prcm_irq β€” bestie, it's literally just the lil descriptor for one single PRCM interrupt bit. one bit. that's her whole job. and she ate ✨


πŸŽ€ SYNOPSIS πŸŽ€

struct omap_prcm_irq {
    const char *name;
    unsigned int offset;
    bool priority;
};

πŸ¦‹ Members πŸ¦‹

  • name β€” a short lil name that says what kind of interrupt this is, like "wkup" or "io" 🏷️
  • offset β€” the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs. yes, shift. as in bit position. iykyk πŸ’…
  • priority β€” the whole question: should this interrupt get handled before the ones where priority=false? main character energy or background extra, you decide πŸ‘‘

🌸 Description 🌸

so this struct describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers β€” that's the whole vibe. 🫢

now here's the tea: on systems with multiple PRM MPU IRQ registers, the bitfields that get read from the registers are concatenated. so on those systems offset could legitimately be > 31 and that's not a bug, that's just how the concatenation goes down. if you wanna know more, go look at omap_prm_irq_handler 😌

and listen β€” I/O ring interrupts should have priority set to true. no cap. do it. πŸ”₯


⭐ SEE ALSO ⭐

  • Kernel file ./arch/arm/mach-omap2/prcm-common.h
  • omap_test_timeout(9)
  • struct omap_prcm_irq_setup(9)
  • struct omap_prcm_init_data(9)

ok that's the whole page, go be iconic with your interrupt bits πŸ’– this came from ./arch/arm/mach-omap2, dated October 2026, and it's the struct omap_prcm_irq(9) page β€” mwah, love u, bye πŸ§šβ€β™€οΈπŸŽ€

πŸ“¦ where this page comes from