STRUCT NT35510_CONFIG(9)

📦 version 7.3.1, in nixpkgs unstable

🌸 NAME 🌸

struct nt35510_config — the display-specific NT35510 configuration. Bestie, welcome to the Kernel API Manual: this is the struct nt35510_config(9) page, and we’re going field by field like it’s a very niche unboxing. 💅✨

🌈 SYNOPSIS 🌈

Okay so the struct looks exactly like this, no cap:

struct nt35510_config {
    u32 width_mm;
    u32 height_mm;
    const struct drm_display_mode mode;
    unsigned long mode_flags;
    u32 cmds;
    u8 avdd[NT35510_P1_AVDD_LEN];
    u8 bt1ctr[NT35510_P1_BT1CTR_LEN];
    u8 avee[NT35510_P1_AVEE_LEN];
    u8 bt2ctr[NT35510_P1_BT2CTR_LEN];
    u8 vcl[NT35510_P1_VCL_LEN];
    u8 bt3ctr[NT35510_P1_BT3CTR_LEN];
    u8 vgh[NT35510_P1_VGH_LEN];
    u8 bt4ctr[NT35510_P1_BT4CTR_LEN];
    u8 vgl[NT35510_P1_VGL_LEN];
    u8 bt5ctr[NT35510_P1_BT5CTR_LEN];
    u8 vgp[NT35510_P1_VGP_LEN];
    u8 vgn[NT35510_P1_VGN_LEN];
    u8 vcmoff[NT35510_P1_VCMOFF_LEN];
    u8 dopctr[NT35510_P0_DOPCTR_LEN];
    u8 madctl;
    u8 sdhdtctr;
    u8 gseqctr[NT35510_P0_GSEQCTR_LEN];
    u8 sdeqctr[NT35510_P0_SDEQCTR_LEN];
    u8 sdvpctr;
    u16 t1;
    u8 vbp;
    u8 vfp;
    u8 psel;
    u8 dpmctr12[NT35510_P0_DPMCTR12_LEN];
    u8 gamma_corr_pos_r[NT35510_P1_GAMMA_LEN];
    u8 gamma_corr_pos_g[NT35510_P1_GAMMA_LEN];
    u8 gamma_corr_pos_b[NT35510_P1_GAMMA_LEN];
    u8 gamma_corr_neg_r[NT35510_P1_GAMMA_LEN];
    u8 gamma_corr_neg_g[NT35510_P1_GAMMA_LEN];
    u8 gamma_corr_neg_b[NT35510_P1_GAMMA_LEN];
    u8 wrdisbv;
    u8 wrctrld;
    u8 wrcabc;
    u8 wrcabcmb;
};

🎀 Members 🎀

Each member is doing its own iconic thing. In order, bestie:

  • width_mm — physical panel width [mm] 🦋
  • height_mm — physical panel height [mm] 🦋
  • mode — the display mode. This is only relevant outside the panel in video mode: in command mode this is configuring the internal timing in the display controller. ⏱️
  • mode_flags — DSI operation mode related flags 🌈
  • cmds — enable DSI commands 🎀
  • avdd — setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V in 0.1V steps; the default is 0x05 which means 6.0V. 💖
  • bt1ctr — setting for boost power control for the AVDD step-up circuit (1)
    • bits 0..2 in the lower nibble control PCK, the booster clock frequency for the step-up circuit: 0 = Hsync/32 1 = Hsync/16 2 = Hsync/8 3 = Hsync/4 4 = Hsync/2 5 = Hsync 6 = Hsync x 2 7 = Hsync x 4
    • bits 4..6 in the upper nibble control BTP, the boosting amplification for the step-up circuit: 0 = Disable 1 = 1.5 x VDDB 2 = 1.66 x VDDB 3 = 2 x VDDB 4 = 2.5 x VDDB 5 = 3 x VDDB
    • The defaults are 4 and 4 yielding 0x44
  • avee — setting for AVEE ranging from 0x00 = -6.5V to 0x14 = -4.5V in 0.1V steps; the default is 0x05 which means -6.0V. 💖
  • bt2ctr — setting for boost power control for the AVEE step-up circuit (2)
    • bits 0..2 in the lower nibble controls NCK, the booster clock frequency, the values are the same as for PCK in bt1ctr.
    • bits 4..5 in the upper nibble controls BTN, the boosting amplification for the step-up circuit: 0 = Disable 1 = -1.5 x VDDB 2 = -2 x VDDB 3 = -2.5 x VDDB 4 = -3 x VDDB
    • The defaults are 4 and 3 yielding 0x34
  • vcl — setting for VCL ranging from 0x00 = -2.5V to 0x11 = -4.0V in 1V steps, the default is 0x00 which means -2.5V. 💖
  • bt3ctr — setting for boost power control for the VCL step-up circuit (3)
    • bits 0..2 in the lower nibble controls CLCK, the booster clock frequency, the values are the same as for PCK in bt1ctr.
    • bits 4..5 in the upper nibble controls BTCL, the boosting amplification for the step-up circuit: 0 = Disable 1 = -0.5 x VDDB 2 = -1 x VDDB 3 = -2 x VDDB
    • The defaults are 4 and 2 yielding 0x24
  • vgh — setting for VGH ranging from 0x00 = 7.0V to 0x0B = 18.0V in 1V steps, the default is 0x08 which means 15V. 💖
  • bt4ctr — setting for boost power control for the VGH step-up circuit (4)
    • bits 0..2 in the lower nibble controls HCK, the booster clock frequency, the values are the same as for PCK in bt1ctr.
    • bits 4..5 in the upper nibble controls BTH, the boosting amplification for the step-up circuit: 0 = AVDD + VDDB 1 = AVDD - AVEE 2 = AVDD - AVEE + VDDB 3 = AVDD x 2 - AVEE
    • The defaults are 4 and 3 yielding 0x34
  • vgl — setting for VGL ranging from 0x00 = -2V to 0x0f = -15V in 1V steps, the default is 0x08 which means -10V. 💖
  • bt5ctr — setting for boost power control for the VGL step-up circuit (5)
    • bits 0..2 in the lower nibble controls LCK, the booster clock frequency, the values are the same as for PCK in bt1ctr.
    • bits 4..5 in the upper nibble controls BTL, the boosting amplification for the step-up circuit: 0 = AVEE + VCL 1 = AVEE - AVDD 2 = AVEE + VCL - AVDD 3 = AVEE x 2 - AVDD
    • The defaults are 3 and 2 yielding 0x32
  • vgp — setting for VGP, the positive gamma divider voltages VGMP the high voltage and VGSP the low voltage. The first byte contains bit 8 of VGMP and VGSP in bits 4 and 0. The second byte contains bit 0..7 of VGMP. The third byte contains bit 0..7 of VGSP. VGMP 0x00 = 3.0V .. 0x108 = 6.3V in steps of 12.5mV. VGSP 0x00 = 0V .. 0x111 = 3.7V in steps of 12.5mV.
  • vgn — setting for VGN, the negative gamma divider voltages, same layout of bytes as vgp.
  • vcmoff — setting the DC VCOM offset voltage
    • The first byte contains bit 8 of VCM in bit 0 and VCMOFFSEL in bit 4.
    • The second byte contains bits 0..7 of VCM.
    • VCMOFFSEL the common voltage offset mode. VCMOFFSEL 0x00 = VCOM .. 0x01 Gamma. The default is 0x00.
    • VCM the VCOM output voltage (VCMOFFSEL = 0) or the internal register offset for gamma voltage (VCMOFFSEL = 1). VCM 0x00 = 0V/0 .. 0x118 = 3.5V/280 in steps of 12.5mV/1step. The default is 0x00 = 0V/0.
  • dopctr — setting optional control for display ERR
    • bits 0..1 in the first byte is the ERR pin output signal setting: 0 = Disable, ERR pin output low; 1 = ERR pin output CRC error only; 2 = ERR pin output ECC error only; 3 = ERR pin output CRC and ECC error. The default is 0.
    • N565 bit 2 in the first byte is the 16-bit/pixel format selection: 0 = R[4:0] + G[5:3] & G[2:0] + B[4:0]; 1 = G[2:0] + R[4:0] & B[4:0] + G[5:3]. The default is 0.
    • DIS_EoTP_HS bit 3 in the first byte is “DSI protocol violation” error reporting: 0 = reporting when error; 1 = not reporting when error.
    • DSIM bit 4 in the first byte is the video mode data type enable: 0 = Video mode data type disable; 1 = Video mode data type enable. The default is 0.
    • DSIG bit 5 in the first byte is the generic r/w data type enable: 0 = Generic r/w disable; 1 = Generic r/w enable. The default is 0.
    • DSITE bit 6 in the first byte is TE line enable: 0 = TE line is disabled; 1 = TE line is enabled. The default is 0.
    • RAMKP bit 7 in the first byte is the frame memory keep/loss in sleep-in mode: 0 = contents loss in sleep-in; 1 = contents keep in sleep-in. The default is 0.
    • CRL bit 1 in the second byte is the source driver data shift direction selection. This bit is XOR operation with bit RSMX of 3600h command. 0 (RMSX = 0) = S1 -> S1440; 0 (RMSX = 1) = S1440 -> S1; 1 (RMSX = 0) = S1440 -> S1; 1 (RMSX = 1) = S1 -> S1440. The default is 0.
    • CTB bit 2 in the second byte is the vertical scanning direction selection for gate control signals. This bit is XOR operation with bit ML of 3600h command. 0 (ML = 0) = Forward (top -> bottom); 0 (ML = 1) = Reverse (bottom -> top); 1 (ML = 0) = Reverse (bottom -> top); 1 (ML = 1) = Forward (top -> bottom). The default is 0.
    • CRGB bit 3 in the second byte is RGB-BGR order selection. This bit is XOR operation with bit RGB of 3600h command. 0 (RGB = 0) = RGB/Normal; 0 (RGB = 1) = BGR/RB swap; 1 (RGB = 0) = BGR/RB swap; 1 (RGB = 1) = RGB/Normal. The default is 0.
    • TE_PWR_SEL bit 4 in the second byte is the TE output voltage level selection (only valid when DSTB_SEL = 0 or DSTB_SEL = 1, VSEL = High and VDDI = 1.665~3.3V). 0 = TE output voltage level is VDDI; 1 = TE output voltage level is VDDA. The default is 0.
  • madctl — Memory data access control
    • RSMY bit 0 is flip vertical. Flips the display image top to down. 🦋
    • RSMX bit 1 is flip horizontal. Flips the display image left to right. 🦋
    • MH bit 2 is the horizontal refresh order.
    • RGB bit 3 is the RGB-BGR order. 0 = RGB color sequence; 1 = BGR color sequence.
    • ML bit 4 is the vertical refresh order.
    • MV bit 5 is the row/column exchange.
    • MX bit 6 is the column address order.
    • MY bit 7 is the row address order.
  • sdhdtctr — source output data hold time 0x00..0x3F = 0..31.5us in steps of 0.5us. The default is 0x05 = 2.5us. 💖
  • gseqctr — EQ control for gate signals GFEQ_XX[3:0]: time setting of EQ step for falling edge in steps of 0.5us. The default is 0x07 = 3.5us GREQ_XX[7:4]: time setting of EQ step for rising edge in steps of 0.5us. The default is 0x07 = 3.5us.
  • sdeqctr — Source driver control settings, first byte is 0 for mode 1 and 1 for mode 2. Mode 1 uses two steps and mode 2 uses three steps meaning EQS3 is not used in mode 1. Mode 2 is default. The last three parameters are EQS1, EQS2 and EQS3, setting the rise time for each equalizer step: 0x00 = 0.0 us to 0x0f = 7.5 us in steps of 0.5us. The default is 0x07 = 3.5 us.
  • sdvpctr — power/voltage behaviour during vertical porch time ⚡
  • t1 — the number of pixel clocks on one scanline, range 0x100 (258 ticks) .. 0x3FF (1024 ticks) so the value + 1 clock ticks. ⏱️
  • vbp — vertical back porch toward the PANEL note: not toward the DSI host; these are separate interfaces, in from DSI host and out to the panel. 🫶
  • vfp — vertical front porch toward the PANEL. 🫶
  • psel — pixel clock divisor: 0 = 1, 1 = 2, 2 = 4, 3 = 8. 🎀
  • dpmctr12 — display timing control 12, bestie, and it's packed okurr 💅:
    • Byte 1 bit 4 picks the LVGL voltage level: 0 = VGLX, 1 = VGL_REG
    • Byte 1 bit 1 picks the gate signal mode: 0 = non-overlap, 1 = overlap
    • Byte 1 bit 0 picks the output signal control R/L swap: 0 = normal, 1 = swap all O->E, L->R
    • Byte 2 is the CLW delay clock for CK O/E and CKB O/E signals: 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps
    • Byte 3 is the FTI_H0 delay time for STP O/E signals: 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps
  • gamma_corr_pos_r — red gamma correction parameters, positive 🍓
  • gamma_corr_pos_g — green gamma correction parameters, positive 🍓
  • gamma_corr_pos_b — blue gamma correction parameters, positive 🍓
  • gamma_corr_neg_r — red gamma correction parameters, negative 🌸
  • gamma_corr_neg_g — green gamma correction parameters, negative 🌸
  • gamma_corr_neg_b — blue gamma correction parameters, negative 🌸
  • wrdisbv — write display brightness. 0x00 value means the lowest brightness and 0xff value means the highest brightness. The default is 0x00. 🔅
  • wrctrld — write control display, and every bit is its own little icon ✨:
    • G bit 0 selects gamma curve: 0 = Manual, 1 = Automatic
    • DB bit 1 selects display brightness: 0 = Manual, 1 = Automatic
    • BL bit 2 controls backlight control: 0 = Off, 1 = On
    • DD bit 3 controls display dimming: 0 = Off, 1 = On
    • A bit 4 controls LABC block: 0 = Off, 1 = On
    • BCTRL bit 5 controls brightness block: 0 = Off, 1 = On
  • wrcabc — write content adaptive brightness control. There is possible to use 4 different modes for content adaptive image functionality: 0: Off, 1: User Interface Image (UI-Mode), 2: Still Picture Image (Still-Mode), 3: Moving Picture Image (Moving-Mode). The default is 0. 🎀
  • wrcabcmb — write CABC minimum brightness. Set the minimum brightness value of the display for CABC function. 0x00 value means the lowest brightness for CABC and 0xff value means the highest brightness for CABC. The default is 0x00. 🫶

🌈 Description 🌈

Okay so some of the settings provide an array of bytes, A, B, C — and here's what they mean, no cap:

  • A = normal / idle off mode
  • B = idle on mode
  • C = partial / idle off mode

Gamma correction arrays are 10bit numbers — two consecutive bytes makes out one point on the gamma correction curve. The points are not linearly placed along the X axis, so we get points 0, 1, 3, 5, 7, 11, 15, 23, 31, 47, 63, 95, 127, 128, 160, 192, 208, 224, 232, 240, 244, 248, 250, 252, 254, 255. The voltages tuples form V0, V1, V3 ... V255, with 0x0000 being the lowest voltage and 0x03FF being the highest voltage. 🦋

Each value must be strictly higher than the previous value forming a rising curve like this, iykyk:

^ |                                        V255 |
V254 |                         ....  |                    V5 |
V3 |     V1 | V0 +------------------------------------------->

The details about all settings can be found in the NT35510 Application Note. 📖

👀 SEE ALSO 👀

Kernel file ./drivers/gpu/drm/panel/panel-novatek-nt35510.c and its besties struct nt35510(9), nt35510_setup_power(9), nt35510_setup_display(9). Go read them, they ate. 💅

And that's the whole thing, bestie — this page came straight out of ./drivers/gpu/drm/panel, it's the October 2026 version, and it's literally titled struct nt35510_config(9). Slay, bye! 👑💖

📦 where this page comes from