STRUCT NFC_CFG(9)
π NAME π
Hey bestie, welcome to the struct nfc_cfg(9) page from the Kernel API Manual β and it's literally the Rockchip NAND controller configuration struct. That's the whole vibe: one iconic struct holding the NAND controller's config, offsets, and ECC status bits. No cap π«Ά
β¨ SYNOPSIS β¨
struct nfc_cfg {
enum nfc_type type;
u8 ecc_strengths[NFC_ECC_MAX_MODES];
u32 ecc_cfgs[NFC_ECC_MAX_MODES];
u32 flctl_off;
u32 bchctl_off;
u32 dma_cfg_off;
u32 dma_data_buf_off;
u32 dma_oob_buf_off;
u32 dma_st_off;
u32 bch_st_off;
u32 randmz_off;
u32 int_en_off;
u32 int_clr_off;
u32 int_st_off;
u32 oob0_off;
u32 oob1_off;
struct rk_ecc_cnt_status ecc0;
struct rk_ecc_cnt_status ecc1;
};
π§ Members π§
Okay so here's the member-by-member breakdown, and yes, every single one is important π
typeβ NFC version.ecc_strengthsβ ECC strengths.ecc_cfgsβ ECC config values.flctl_offβ FLCTL register offset.bchctl_offβ BCHCTL register offset.dma_cfg_offβ DMA_CFG register offset.dma_data_buf_offβ DMA_DATA_BUF register offset.dma_oob_buf_offβ DMA_OOB_BUF register offset.dma_st_offβ DMA_ST register offset.bch_st_offβ BCG_ST register offset. Yes, it saysBCG_STexactly β we're keeping it exactly as written, bestie.randmz_offβ RANDMZ register offset.int_en_offβ interrupt enable register offset.int_clr_offβ interrupt clean register offset.int_st_offβ interrupt status register offset.oob0_offβ oob0 register offset.oob1_offβ oob1 register offset.ecc0β represent ECC0 status data.ecc1β represent ECC1 status data.
π SEE ALSO π
- Kernel file
./drivers/mtd/nand/raw/rockchip-nand-controller.c struct rk_ecc_cnt_status(9)
π cute sign-off: this page came from./drivers/mtd/nand/raw, datedOctober 2026, and it's all aboutstruct nfc_cfg(9). Bye bestie β go configure that Rockchip NAND controller and slay π β¨
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms