STRUCT MV_CESA_ENGINE(9)

💅 struct mv_cesa_engine(9) 💅

okay so this is a page from the Kernel API Manual and honestly? it's giving crypto-engine realness. bestie, we're about to get into struct mv_cesa_engine and you're gonna slay this.

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✨ NAME ✨

struct mv_cesa_engine — the CESA engine, periodt 💖

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🎀 SYNOPSIS 🎀

struct mv_cesa_engine {
    int id;
    void __iomem *regs;
    union {
      void __iomem *sram;
      void *sram_pool;
    };
    dma_addr_t sram_dma;
    spinlock_t lock;
    struct crypto_async_request *req;
    struct clk *clk;
    struct clk *zclk;
    size_t max_req_len;
    u32 int_mask;
    struct mv_cesa_dev *cesa;
    struct gen_pool *pool;
    struct crypto_queue queue;
    atomic_t load;
    struct mv_cesa_tdma_chain chain_hw;
    struct mv_cesa_tdma_chain chain_sw;
    struct list_head complete_queue;
    int irq;
 };

like, look at all those fields. the way that this struct just holds everything? main character energy fr fr 👑

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🦋 MEMBERS 🦋

• id — the engine id. that's it, that's the field 🪪
• regs — the engine registers, the actual hardware door 🚪
• {unnamed_union} — it's anonymous. no name. mysterious. iconic 🙈
  • sram — the SRAM memory region 💾
  • sram_pool — the SRAM memory region but pulled from a pool 🏊
• sram_dma — the DMA address of that SRAM memory region ✨
• lock — the engine lock, keep it locked bestie 🔒
• req — the current crypto request, like the one being dealt with right now 📨
• clk — the engine clk ⏰
• zclk — the engine zclk ⏰⏰ (yes there's two, no I will not explain further, it's literally in the struct)
• max_req_len — the maximum chunk length, and the manpage says this is useful to create the TDMA chain 📏
• int_mask — the interrupt mask cache 🎭
• cesa — back-pointer to the parent CESA device, so it knows where it came from 🫶
• pool — the memory pool pointing to the memory region reserved in SRAM 🧺
• queue — the fifo of the pending crypto requests, they're waiting their turn in line 🚶‍♀️
• load — the engine load counter, useful for load balancing, it's literally doing the most ⚖️
• chain_hw — the list of the current tdma descriptors being processed by the hardware. hardware is busy, do not disturb 💀
• chain_sw — the list of the current tdma descriptors that will be submitted to the hardware. the next-up squad 🌸
• complete_queue — the fifo of the processed requests by the engine, aka the finished-it pile ✅
• irq — the interrupt request line, it's giving "notice me" 📣

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🌈 DESCRIPTION 🌈

It's a structure storing CESA engine information. that's the whole vibe. it holds the info. it's the info-holder. no cap 🧚

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🔥 SEE ALSO 🔥

• Kernel file ./drivers/crypto/marvell/cesa/cesa.h
• struct mv_cesa_sec_accel_desc(9)
• struct mv_cesa_skcipher_op_ctx(9)
• struct mv_cesa_hash_op_ctx(9)
• struct mv_cesa_op_ctx(9)
• struct mv_cesa_tdma_desc(9)
• struct mv_cesa_sg_dma_iter(9)
• struct mv_cesa_dma_iter(9)
• struct mv_cesa_tdma_chain(9)
• struct mv_cesa_caps(9)
• struct mv_cesa_dev_dma(9)
• struct mv_cesa_dev(9)
• struct mv_cesa_req_ops(9)
• struct mv_cesa_ctx(9)
• struct mv_cesa_hash_ctx(9)
• enum mv_cesa_req_type(9)
• struct mv_cesa_req(9)
• struct mv_cesa_sg_std_iter(9)
• struct mv_cesa_skcipher_std_req(9)
• struct mv_cesa_skcipher_req(9)
• struct mv_cesa_ahash_std_req(9)
• struct mv_cesa_ahash_dma_req(9)
• struct mv_cesa_ahash_req(9)

like that's the whole friend group right there, go read all of them, iykyk 💜

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and that's the page bestie!! 🫶 this one lives in ./drivers/crypto/marvell/cesa and it's dated October 2026 — so yeah, future-coded of it. mwah, go forth and understand your CESA engines 💅⭐