STRUCT MU3C_IPPC_REGS(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… struct mu3c_ippc_regs(9) πŸ’…

okay bestie, welcome to the Kernel API Manual entry for this little kernel struct πŸ’–. It's giving β€œMTK ssusb ip port control registers” realness, and we're gonna keep every field exactly where it belongs. No cap.

✨ NAME ✨

struct mu3c_ippc_regs β€” MTK ssusb ip port control registers

  • @ip_pw_ctr0~3: ip power and clock control registers
  • @ip_pw_sts1~2: ip power and clock status registers

🌸 SYNOPSIS 🌸

Here's the struct in all its little-endian glory β€” copy it exactly, bestie, every field and every reserved slot included:

struct mu3c_ippc_regs {
    __le32 ip_pw_ctr0;
    __le32 ip_pw_ctr1;
    __le32 ip_pw_ctr2;
    __le32 ip_pw_ctr3;
    __le32 ip_pw_sts1;
    __le32 ip_pw_sts2;
    __le32 reserved0[3];
    __le32 ip_xhci_cap;
    __le32 reserved1[2];
    __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
    __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
    __le32 reserved2;
    __le32 u2_phy_pll;
    __le32 reserved3[33];
};

🫢 Members 🫢

  • ip_xhci_cap β€” ip xHCI capability register
  • u3_ctrl_p[x] β€” ip usb3 port x control register, only low 4bytes are used
  • u2_ctrl_p[x] β€” ip usb2 port x control register, only low 4bytes are used
  • u2_phy_pll β€” usb2 phy pll control register

🌈 SEE ALSO 🌈

Peep the kernel file ./drivers/usb/host/xhci-mtk.h and these related structs: struct mu3h_sch_tt(9), struct mu3h_sch_bw_info(9), struct mu3h_sch_ep_info(9) πŸ‘‘


mwah πŸ’‹ β€” this page comes from source/version ./drivers/usb/host, dated October 2026 πŸŽ€

πŸ“¦ where this page comes from