STRUCT MTK_PINCTRL_DEVDATA(9)

✨ NAME ✨

struct mtk_pinctrl_devdata — bestie, this is the struct that hands over all the HW GPIO related data 💅 that's literally its whole job, "Provide HW GPIO related data", iconic.

🦋 SYNOPSIS 🦋

okay so here's the whole shape of it, no cap, every field exactly where it lives 👑

       struct mtk_pinctrl_devdata {
           const struct mtk_desc_pin       *pins;
           unsigned int                            npins;
           const struct mtk_drv_group_desc *grp_desc;
           unsigned int    n_grp_cls;
           const struct mtk_pin_drv_grp    *pin_drv_grp;
           unsigned int    n_pin_drv_grps;
           const struct mtk_pin_ies_smt_set *spec_ies;
           unsigned int n_spec_ies;
           const struct mtk_pin_spec_pupd_set_samereg *spec_pupd;
           unsigned int n_spec_pupd;
           const struct mtk_pin_ies_smt_set *spec_smt;
           unsigned int n_spec_smt;
           int (*spec_pull_set)(struct regmap *regmap, const struct
       mtk_pinctrl_devdata *devdata, unsigned int pin, bool isup, unsigned int
       r1r0);
           int (*spec_ies_smt_set)(struct regmap *reg, const struct
       mtk_pinctrl_devdata *devdata, unsigned int pin, int value, enum
       pin_config_param arg);
           void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
       unsigned int mode);
           void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
           int (*mt8365_set_clr_mode)(struct regmap *regmap, unsigned int bit,
       unsigned int reg_pullen, unsigned int reg_pullsel, bool enable, bool
       isup);
           unsigned int dir_offset;
           unsigned int ies_offset;
           unsigned int smt_offset;
           unsigned int pullen_offset;
           unsigned int pullsel_offset;
           unsigned int dout_offset;
           unsigned int din_offset;
           unsigned int pinmux_offset;
           unsigned short type1_start;
           unsigned short type1_end;
           unsigned char  port_shf;
           unsigned char  port_mask;
           unsigned char  port_align;
           struct mtk_eint_hw eint_hw;
           struct mtk_eint_regs *eint_regs;
           unsigned int mode_mask;
           unsigned int mode_per_reg;
           unsigned int mode_shf;
        };

🎀 Members 🎀

time for the vibe check on each member, let's go 💖

• pins — an array that describes all the pins the pin controller affects 🌸 like the full guest list, everybody's in here.
• npins — the number of entries in pins. literally just the headcount 🫶
• grp_desc — the driving group info. the group chat bio, if u will ✨
• pin_drv_grp — the driving group for all pins. yes, all of them 💅
• spec_ies — special pin setting for input enable 👑
• n_spec_ies — number of entries in spec_ies ⭐
• spec_pupd — special pull up/down setting 🎀
• n_spec_pupd — number of entries in spec_pupd 🌈
• spec_smt — special pin setting for schmitt 🦋
• n_spec_smt — number of entries in spec_smt 💜
• spec_pull_set — okay so each SoC may have special pins for pull up/down setting, and these pins' pull setting are very different — they have a separate pull up/down bit, plus the R0 and R1 resistor bit, so they need special pull setting, fr fr. if the special setting is success, this should return 0, otherwise it should return a non-zero value 😭 (yes bestie, 0 means slay, non-zero means something went sideways).
• spec_ies_smt_set — some pins are irregular: their input enable and smt control register are discontinuous, but they are mapping together. that means when the user sets smt, input enable is set at the same time 🫠 so they also need special control. if special control is success, this should return 0, otherwise return a non-zero value 💀
• spec_pinmux_set — in some cases there are two pinmux functions that share the same value in the same segment of the pinmux control register. so if the user wants to use one of the two functions, they need an extra bit setting to select the right one 🙈 the drama of it all.
• spec_dir_set — in very few SoCs, the direction control registers are not arranged continuously, they may be cut to parts, so they need special dir setting 🧚 rare but real.
• mt8365_set_clr_mode — in mt8365, some pins won't set correcty because they need to use the main R/W register to read/update/write the modes instead of the SET/CLR register 😤 (that's the manpage's spelling of "correcty", we keep it, we respect it).
• dir_offset — the direction register offset. where it's at 📍
• pullen_offset — the pull-up/pull-down enable register offset 🌸
• pinmux_offset — the pinmux register offset ✨
• type1_start — some chips have two base addresses for the pull select register, meaning some pins use the first address and others use the second. this member records the start of the pin number to use the second address 👑 (so this is where the second-address era begins).
• type1_end — the end of the pin number to use the second address 🎀 the era ends here.
• port_shf — the shift between two registers 🦋 the gap, the distance, the space between.
• port_mask — the mask of the register 💅
• port_align — provide clear register and set register step ⭐

🔥 SEE ALSO 🔥

• Kernel file ./drivers/pinctrl/mediatek/pinctrl-mtk-common.h
• struct mtk_drv_group_desc(9)
• struct mtk_pin_drv_grp(9)
• struct mtk_pin_spec_pupd_set_samereg(9)

and that's the whole page bestie, go read the kernel source, iykyk 🌈🫶

source/version: ./drivers/pinctrl/mediatek — dated October 2026, from the Kernel API Manual, all about struct mtk_pinctrl_devdata(9) 💖 mwah, go forth and configure those pins 👑✨