STRUCT MTK_DPI_CONF(9)
π struct mtk_dpi_conf(9) π
okay bestie, welcome to the Kernel API Manual moment for struct mtk_dpi_conf β literally the configuration of mediatek dpi, and yes she has a lot of fields, but weβre gonna get through every single one together. π«Άβ¨
πΈ NAME πΈ
struct mtk_dpi_conf β Configuration of mediatek dpi. Thatβs the whole vibe, no cap. π
π¦ SYNOPSIS π¦
okay so hereβs the struct in all her glory, copied exactly so you can trust it:
struct mtk_dpi_conf {
const struct mtk_dpi_factor *dpi_factor;
const u8 num_dpi_factor;
u32 reg_h_fre_con;
u32 max_clock_khz;
bool edge_sel_en;
const u32 *output_fmts;
u32 num_output_fmts;
bool is_ck_de_pol;
bool swap_input_support;
bool support_direct_pin;
u32 dimension_mask;
u32 hvsize_mask;
u32 channel_swap_shift;
u32 yuv422_en_bit;
u32 csc_enable_bit;
u32 input_2p_en_bit;
u32 pixels_per_iter;
bool edge_cfg_in_mmsys;
bool clocked_by_hdmi;
bool output_1pixel;
};
π Members π
every field, bestie β no skips, no cap:
dpi_factorβ SoC-specific pixel clock PLL factor values. iconic.num_dpi_factorβ Number of pixel clock PLL factor values. β¨reg_h_fre_conβ Register address of frequency control. πmax_clock_khzβ Max clock frequency supported for this SoCs in khz units.edge_sel_enβ Enable of edge selection.output_fmtsβ Array of supported output formats. πnum_output_fmtsβ Quantity of supported output formats.is_ck_de_polβ Support CK/DE polarity. πswap_input_supportβ Support input swap function.support_direct_pinβ IP supports direct connection to dpi panels.dimension_maskβ Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift). πhvsize_maskβ Mask of HSIZE and VSIZE mask (no shift).channel_swap_shiftβ Shift value of channel swap.yuv422_en_bitβ Enable bit of yuv422.csc_enable_bitβ Enable bit of CSC.input_2p_en_bitβ Enable bit for input two pixel per round feature. If present, implies that the feature must be enabled. important bestie!pixels_per_iterβ Quantity of transferred pixels per iteration.edge_cfg_in_mmsysβ If the edge configuration for DPI's output needs to be set in MMSYS.clocked_by_hdmiβ HDMI IP outputs clock to dpi_pixel_clk input clock, needed for DPI registers access. π°οΈoutput_1pixelβ Enable outputting one pixel per round; if the input is two pixel per round, the DPI hardware will internally transform it to 1T1P. π₯
π SEE ALSO π
- Kernel file
./drivers/gpu/drm/mediatek/mtk_dpi.cπ
okay bye bestie! this pageβs source/version is ./drivers/gpu/drm/mediatek, itβs dated October 2026, and it stars struct mtk_dpi_conf(9) β mwah π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms