STRUCT MTK_DPI_CONF(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– struct mtk_dpi_conf(9) πŸ’–

okay bestie, welcome to the Kernel API Manual moment for struct mtk_dpi_conf β€” literally the configuration of mediatek dpi, and yes she has a lot of fields, but we’re gonna get through every single one together. 🫢✨


🌸 NAME 🌸

struct mtk_dpi_conf β€” Configuration of mediatek dpi. That’s the whole vibe, no cap. πŸ’…


πŸ¦‹ SYNOPSIS πŸ¦‹

okay so here’s the struct in all her glory, copied exactly so you can trust it:

       struct mtk_dpi_conf {
           const struct mtk_dpi_factor *dpi_factor;
           const u8 num_dpi_factor;
           u32 reg_h_fre_con;
           u32 max_clock_khz;
           bool edge_sel_en;
           const u32 *output_fmts;
           u32 num_output_fmts;
           bool is_ck_de_pol;
           bool swap_input_support;
           bool support_direct_pin;
           u32 dimension_mask;
           u32 hvsize_mask;
           u32 channel_swap_shift;
           u32 yuv422_en_bit;
           u32 csc_enable_bit;
           u32 input_2p_en_bit;
           u32 pixels_per_iter;
           bool edge_cfg_in_mmsys;
           bool clocked_by_hdmi;
           bool output_1pixel;
        };

πŸŽ€ Members πŸŽ€

every field, bestie β€” no skips, no cap:

  • dpi_factor β€” SoC-specific pixel clock PLL factor values. iconic.
  • num_dpi_factor β€” Number of pixel clock PLL factor values. ✨
  • reg_h_fre_con β€” Register address of frequency control. πŸ“
  • max_clock_khz β€” Max clock frequency supported for this SoCs in khz units.
  • edge_sel_en β€” Enable of edge selection.
  • output_fmts β€” Array of supported output formats. 🌈
  • num_output_fmts β€” Quantity of supported output formats.
  • is_ck_de_pol β€” Support CK/DE polarity. πŸ’…
  • swap_input_support β€” Support input swap function.
  • support_direct_pin β€” IP supports direct connection to dpi panels.
  • dimension_mask β€” Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift). πŸ“
  • hvsize_mask β€” Mask of HSIZE and VSIZE mask (no shift).
  • channel_swap_shift β€” Shift value of channel swap.
  • yuv422_en_bit β€” Enable bit of yuv422.
  • csc_enable_bit β€” Enable bit of CSC.
  • input_2p_en_bit β€” Enable bit for input two pixel per round feature. If present, implies that the feature must be enabled. important bestie!
  • pixels_per_iter β€” Quantity of transferred pixels per iteration.
  • edge_cfg_in_mmsys β€” If the edge configuration for DPI's output needs to be set in MMSYS.
  • clocked_by_hdmi β€” HDMI IP outputs clock to dpi_pixel_clk input clock, needed for DPI registers access. πŸ•°οΈ
  • output_1pixel β€” Enable outputting one pixel per round; if the input is two pixel per round, the DPI hardware will internally transform it to 1T1P. πŸ”₯

🌈 SEE ALSO 🌈

  • Kernel file ./drivers/gpu/drm/mediatek/mtk_dpi.c πŸ‘€

okay bye bestie! this page’s source/version is ./drivers/gpu/drm/mediatek, it’s dated October 2026, and it stars struct mtk_dpi_conf(9) β€” mwah πŸ’‹

πŸ“¦ where this page comes from