STRUCT MMP_PDMA_OPS(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

🌸 struct mmp_pdma_ops(9) 🌸

okay so bestie, welcome to the Kernel API Manual ✨ β€” this is the page for struct mmp_pdma_ops, and it's basically the ops table for the MMP PDMA controller. it's giving "here's all the function pointers and config bits you need" energy, and honestly? iconic of it. πŸ’…


πŸ’– NAME πŸ’–

struct mmp_pdma_ops β€” the Operations for the MMP PDMA controller 🫢


✨ SYNOPSIS ✨

struct mmp_pdma_ops {
    void (*write_next_addr)(struct mmp_pdma_phy *phy, dma_addr_t addr);
    u64 (*read_src_addr)(struct mmp_pdma_phy *phy);
    u64 (*read_dst_addr)(struct mmp_pdma_phy *phy);
    void (*set_desc_next_addr)(struct mmp_pdma_desc_hw *desc, dma_addr_t
addr);
    void (*set_desc_src_addr)(struct mmp_pdma_desc_hw *desc, dma_addr_t
addr);
    void (*set_desc_dst_addr)(struct mmp_pdma_desc_hw *desc, dma_addr_t
addr);
    u64 (*get_desc_src_addr)(const struct mmp_pdma_desc_hw *desc);
    u64 (*get_desc_dst_addr)(const struct mmp_pdma_desc_hw *desc);
    u32 run_bits;
    u32 dma_width;
    u32 drcmr_ext_base;
 };

like, look at all those function pointers. so organized. we love a struct that knows what it wants πŸ’œ


πŸŽ€ Members πŸŽ€

okay so here's the whole cast, member by member, no cap:

  • write_next_addr β€” the function that programs the address of the next descriptor into DDADR/DDADRH πŸ”₯
  • read_src_addr β€” the function that reads the source address from DSADR/DSADRH
  • read_dst_addr β€” the function that reads the destination address from DTADR/DTADRH
  • set_desc_next_addr β€” the function that sets the next descriptor address in the descriptor
  • set_desc_src_addr β€” the function that sets the source address in the descriptor
  • set_desc_dst_addr β€” the function that sets the destination address in the descriptor
  • get_desc_src_addr β€” the function that gets the source address from the descriptor
  • get_desc_dst_addr β€” the function that gets the destination address from the descriptor
  • run_bits β€” the control bits in the DCSR register for channel start/stop πŸ‘‘
  • dma_width β€” the DMA addressing width in bits (32 or 64). this one determines the DMA mask capability of the controller hardware β€” important, bestie, don't sleep on it 🌈
  • drcmr_ext_base β€” the base DRCMR address for extended requests πŸ¦‹

πŸ’« Description πŸ’«

so the page groups things into three little vibes:

Hardware Register Operations (read/write hardware registers):

Descriptor Memory Operations (manipulate descriptor structs in memory):

Controller Configuration:

like yes, those are the three lanes this struct runs in. 🧚


πŸ” SEE ALSO πŸ”

  • Kernel file ./drivers/dma/mmp_pdma.c

and that's the whole page, bestie, you ate it πŸ’– if you ever need to find it again it lives in ./drivers/dma, dated October 2026, and honestly the version is right there with it β€” fr fr, go read the source, it's literally one file down. πŸ“

πŸ“¦ where this page comes from