STRUCT MARVELL_NFC(9)
π struct marvell_nfc(9) β the Kernel API Manual, but make it cute
okay so bestie, welcome to the glow-up of struct marvell_nfc(9) from the Kernel API Manual β¨ this is the little struct that holds literally everything the Marvell NAND controller needs to know about itself. like its whole personality in one C struct. slay π
β¨ NAME β¨
struct marvell_nfc β stores Marvell NAND controller information π¦
that's it, that's the job. it's a storage struct. it stores. iconic behavior honestly.
π SYNOPSIS π
here's the whole vibe, character for character, no cap:
struct marvell_nfc {
struct nand_controller controller;
struct device *dev;
void __iomem *regs;
struct clk *core_clk;
struct clk *reg_clk;
struct completion complete;
unsigned long assigned_cs;
struct list_head chips;
struct nand_chip *selected_chip;
const struct marvell_nfc_caps *caps;
bool use_dma;
struct dma_chan *dma_chan;
u8 *dma_buf;
};
look at her. thirteen members. main character energy fr fr π
πΈ Members πΈ
okay let's meet the cast one by one, bestie, no skipping, we're doing all of them:
controllerβ the base controller structure π the foundation, the blueprint, the mother.devβ the parent device, and yes she's the one used to print error messages π so when something breaks, this is who's doing the yelling.regsβ the NAND controller registers π the actual hardware knobs and dials.core_clkβ the core clock β° ticking away, keeping time.reg_clkβ the registers clock β¨ a whole separate clock, just for the registers. she's got her own thing going on.completeβ a completion object to wait for NAND controller events π«Ά it's giving "hold please, waiting for the hardware to text back."assigned_csβ a bitmask describing already assigned CS lines π bitmask! so each bit is a little "taken" flag. very efficient, very demure.chipsβ a list containing all the NAND chips attached to this NAND controller π the whole friend group in one list.selected_chipβ the currently selected target chip π the one getting the spotlight right now. main character of the moment.capsβ NAND controller capabilities for each compatible string π the talents, the skillset, the rΓ©sumΓ©.use_dmaβ whether DMA is used π₯ bool so it's a yes or a no, no in-between.dma_chanβ the DMA channel, and heads up bestie, NFCv1 only πdma_bufβ a 32-bit aligned buffer for DMA transfers, also NFCv1 only π so don't come looking for it on other versions, it's not there.
lowkey important:dma_chananddma_bufare NFCv1-only. that's not me being dramatic, that's just the facts π
π¦ SEE ALSO π¦
go read these next, bestie, they're all in the same friend group:
- Kernel file
./drivers/mtd/nand/raw/marvell_nand.c struct marvell_hw_ecc_layout(9)struct marvell_nand_chip_sel(9)struct marvell_nand_chip(9)struct marvell_nfc_caps(9)struct marvell_nfc_timings(9)TO_CYCLES(9)struct marvell_nfc_op(9)
that's the whole page, periodt π
this little icon lives in ./drivers/mtd/nand/raw and the version/date on her birth certificate says October 2026 π mwah, go read the kernel source, ily, bye π«Άπ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms