STRUCT MARVELL_NFC(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… struct marvell_nfc(9) β€” the Kernel API Manual, but make it cute

okay so bestie, welcome to the glow-up of struct marvell_nfc(9) from the Kernel API Manual ✨ this is the little struct that holds literally everything the Marvell NAND controller needs to know about itself. like its whole personality in one C struct. slay πŸ’–


✨ NAME ✨

struct marvell_nfc β€” stores Marvell NAND controller information πŸ¦‹

that's it, that's the job. it's a storage struct. it stores. iconic behavior honestly.


πŸŽ€ SYNOPSIS πŸŽ€

here's the whole vibe, character for character, no cap:

struct marvell_nfc {
    struct nand_controller controller;
    struct device *dev;
    void __iomem *regs;
    struct clk *core_clk;
    struct clk *reg_clk;
    struct completion complete;
    unsigned long assigned_cs;
    struct list_head chips;
    struct nand_chip *selected_chip;
    const struct marvell_nfc_caps *caps;
    bool use_dma;
    struct dma_chan *dma_chan;
    u8 *dma_buf;
 };

look at her. thirteen members. main character energy fr fr πŸ‘‘


🌸 Members 🌸

okay let's meet the cast one by one, bestie, no skipping, we're doing all of them:

  • controller β€” the base controller structure πŸ’… the foundation, the blueprint, the mother.
  • dev β€” the parent device, and yes she's the one used to print error messages 😭 so when something breaks, this is who's doing the yelling.
  • regs β€” the NAND controller registers 🌈 the actual hardware knobs and dials.
  • core_clk β€” the core clock ⏰ ticking away, keeping time.
  • reg_clk β€” the registers clock ✨ a whole separate clock, just for the registers. she's got her own thing going on.
  • complete β€” a completion object to wait for NAND controller events 🫢 it's giving "hold please, waiting for the hardware to text back."
  • assigned_cs β€” a bitmask describing already assigned CS lines πŸ‘‘ bitmask! so each bit is a little "taken" flag. very efficient, very demure.
  • chips β€” a list containing all the NAND chips attached to this NAND controller πŸ“ the whole friend group in one list.
  • selected_chip β€” the currently selected target chip 🌟 the one getting the spotlight right now. main character of the moment.
  • caps β€” NAND controller capabilities for each compatible string πŸ’œ the talents, the skillset, the rΓ©sumΓ©.
  • use_dma β€” whether DMA is used πŸ”₯ bool so it's a yes or a no, no in-between.
  • dma_chan β€” the DMA channel, and heads up bestie, NFCv1 only πŸ™ˆ
  • dma_buf β€” a 32-bit aligned buffer for DMA transfers, also NFCv1 only πŸ’€ so don't come looking for it on other versions, it's not there.
lowkey important: dma_chan and dma_buf are NFCv1-only. that's not me being dramatic, that's just the facts 😌

πŸ¦‹ SEE ALSO πŸ¦‹

go read these next, bestie, they're all in the same friend group:

  • Kernel file ./drivers/mtd/nand/raw/marvell_nand.c
  • struct marvell_hw_ecc_layout(9)
  • struct marvell_nand_chip_sel(9)
  • struct marvell_nand_chip(9)
  • struct marvell_nfc_caps(9)
  • struct marvell_nfc_timings(9)
  • TO_CYCLES(9)
  • struct marvell_nfc_op(9)

that's the whole page, periodt πŸ’… this little icon lives in ./drivers/mtd/nand/raw and the version/date on her birth certificate says October 2026 🌈 mwah, go read the kernel source, ily, bye πŸ«ΆπŸ’–

πŸ“¦ where this page comes from