STRUCT MARVELL_NAND_CHIP_SEL(9)

💅 struct marvell_nand_chip_sel(9) — Kernel API Manual 💅

okay bestie, this is the Kernel API Manual page for struct marvell_nand_chip_sel, and it is literally a CS line description. no cap, we're going through every field and note. 🎀

🎀 NAME 🎀

struct marvell_nand_chip_sel — CS line description 💅

✨ SYNOPSIS ✨

       struct marvell_nand_chip_sel {
           unsigned int cs;
           u32 ndcb0_csel;
           unsigned int rb;
        };

💖 Members 💖

• cs — the wanted CE lane. 🎯
• ndcb0_csel — value of the NDCB0 register, with or without the flag selecting the wanted CE lane. This is set once when the Device Tree is probed. ✨
• rb — the Ready/Busy pin for the flash chip. ⭐

🌸 Description 🌸

okay so the Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection is made by a field in the NDCB0 register, and in another field in the NDCB2 register. The datasheet describes the logic with an error: the ADDR5 field is once declared at the beginning of NDCB2, and another time at its end. Because the ADDR5 field of NDCB2 may be used by other bytes, it would be more logical to use the last bit of this field instead of the first ones. 👑

Not me side-eyeing that datasheet error 😭 but anyway, that's the whole vibe.

🦋 SEE ALSO 🦋

• Kernel file: ./drivers/mtd/nand/raw/marvell_nand.c
• struct marvell_hw_ecc_layout(9)
• struct marvell_nand_chip(9)
• struct marvell_nfc_caps(9)
• struct marvell_nfc(9)
• struct marvell_nfc_timings(9)
• TO_CYCLES(9)
• struct marvell_nfc_op(9)

xoxo, your Kernel API Manual bestie 💖 — source/version: ./drivers/mtd/nand/raw, date: October 2026. Periodt. 🫶