STRUCT MARVELL_HW_ECC_LAYOUT(9)

💅 struct marvell_hw_ecc_layout(9) — the Kernel API Manual, bestie edition 🎀

okay so you opened the Kernel API Manual and landed on this page, and honestly? it's kind of a baddie. this is struct marvell_hw_ecc_layout — the literal layout of Marvell ECC. it's giving blueprint energy. let's get into it 💖

---

✨ NAME ✨

struct marvell_hw_ecc_layout — layout of Marvell ECC. that's it, that's the whole vibe check.

---

🌸 SYNOPSIS 🌸

struct marvell_hw_ecc_layout {
    int writesize;
    int chunk;
    int strength;
    int nchunks;
    int full_chunk_cnt;
    int data_bytes;
    int spare_bytes;
    int ecc_bytes;
    int last_data_bytes;
    int last_spare_bytes;
    int last_ecc_bytes;
 };

look at her. eleven ints and not a single one out of place. main character struct fr fr 👑

---

🦋 Members 🦋

bestie these are the fields, and every single one is iconic in her own way:

• writesize — the full page size that this layout applies to ✨
• chunk — the ECC chunk size you want, and the layout applies to that. lowkey the size of one chunk, conceptually 🎀
• strength — the ECC strength you want, measured per chunk size bytes, and again — the layout applies to that 💪
• nchunks — total number of chunks, no cap 🧮
• full_chunk_cnt — the number of full-sized chunks. which is literally the number of times this pattern repeats: (data_bytes + spare_bytes + ecc_bytes). she's a counter of repetitions, she's doing great 💅
• data_bytes — how many data bytes per chunk 🍓
• spare_bytes — how many spare bytes per chunk 🌈
• ecc_bytes — how many ecc bytes per chunk ⭐
• last_data_bytes — how many data bytes are in that last chunk (yes, the last chunk is special, we'll get there) 🙈
• last_spare_bytes — how many spare bytes are in the last chunk 💜
• last_ecc_bytes — how many ecc bytes are in the last chunk 🔥

---

💀 Description 💀

so here's the tea. the Marvell ECC engine works differently than all the others — not better, not worse, just different, periodt.

why? to limit the size of the IP, the hardware engineers chose to set a fixed strength at 16 bits per subpage. that's the hardware's whole personality, she's fixed at it.

then, depending on the desired strength that the NAND chip actually needs, a particular layout gets defined — one that mixes data / spare / ecc — and that layout may possibly have a last chunk smaller than the others. that's the plot twist 🫶

ngl that last chunk being tinier than her sisters is the detail everyone forgets. don't be the one who forgets 💀

---

🔥 SEE ALSO 🔥

go read these next, bestie, they're all in the same friend group:

• the kernel file ./drivers/mtd/nand/raw/marvell_nand.c — the source material 🧚
• struct marvell_nand_chip_sel(9)
• struct marvell_nand_chip(9)
• struct marvell_nfc_caps(9)
• struct marvell_nfc(9)
• struct marvell_nfc_timings(9)
• TO_CYCLES(9)
• struct marvell_nfc_op(9)

---

✨ mwah ✨ that's the page. she lives at ./drivers/mtd/nand/raw, she's dated October 2026, and she signs off as struct marve...w_ecc_layout(9) — truncated name and all, and honestly? iconic. go ship it, bestie 💖🎀🦋