STRUCT IWL_TRANS_PCIE(9)
π struct iwl_trans_pcie(9) β the PCIe transport's whole personality, bestie
okay so like. this is the Kernel API Manual page. the struct lives in ./drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/internal.h and honestly it's giving main character energy β it holds literally every scrap of PCIe-transport-specific data. buckle up π
β¨ NAME β¨
struct iwl_trans_pcie β PCIe transport specific data. that's it. that's the vibe. π
πΈ SYNOPSIS πΈ
struct iwl_trans_pcie {
struct iwl_rxq *rxq;
struct iwl_rx_mem_buffer *rx_pool;
struct iwl_rx_mem_buffer **global_table;
struct iwl_rb_allocator rba;
union {
struct iwl_context_info *ctxt_info;
struct iwl_context_info_v2 *ctxt_info_v2;
};
struct iwl_prph_info *prph_info;
struct iwl_prph_scratch *prph_scratch;
void *iml;
size_t iml_len;
dma_addr_t ctxt_info_dma_addr;
dma_addr_t prph_info_dma_addr;
dma_addr_t prph_scratch_dma_addr;
dma_addr_t iml_dma_addr;
struct iwl_trans *trans;
struct net_device *napi_dev;
__le32 *ict_tbl;
dma_addr_t ict_tbl_dma;
int ict_index;
bool use_ict;
bool is_down, opmode_down;
s8 debug_rfkill;
struct isr_statistics isr_stats;
spinlock_t irq_lock;
struct mutex mutex;
u32 inta_mask;
u32 scd_base_addr;
struct iwl_dma_ptr kw;
struct iwl_dram_regions pnvm_data;
struct iwl_dram_regions reduced_tables_data;
struct iwl_txq *txq_memory;
struct pci_dev *pci_dev;
u8 __iomem *hw_base;
bool ucode_write_complete;
enum {
IWL_SX_INVALID = 0,
IWL_SX_WAITING,
IWL_SX_ERROR,
IWL_SX_COMPLETE,
} sx_state;
wait_queue_head_t ucode_write_waitq;
wait_queue_head_t sx_waitq;
u16 num_rx_bufs;
u32 rx_page_order;
u32 rx_buf_bytes;
u32 supported_dma_mask;
spinlock_t alloc_page_lock;
struct page *alloc_page;
u32 alloc_page_used;
spinlock_t reg_lock;
bool cmd_hold_nic_awake;
#ifdef CONFIG_IWLWIFI_DEBUGFS;
struct cont_rec fw_mon_data;
#endif;
struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
bool msix_enabled;
u8 shared_vec_mask;
u32 alloc_vecs;
u32 def_irq;
u32 fh_init_mask;
u32 hw_init_mask;
u32 fh_mask;
u32 hw_mask;
cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
u16 tx_cmd_queue_size;
bool in_rescan;
void *base_rb_stts;
dma_addr_t base_rb_stts_dma;
enum iwl_pcie_fw_reset_state fw_reset_state;
wait_queue_head_t fw_reset_waitq;
enum iwl_pcie_imr_status imr_status;
wait_queue_head_t imr_waitq;
char rf_name[32];
struct iwl_pcie_txqs txqs;
s8 me_present;
struct delayed_work me_recheck_wk;
struct iwl_dma_ptr invalid_tx_cmd;
wait_queue_head_t wait_command_queue;
struct kmem_cache *dev_cmd_pool;
char dev_cmd_pool_name[50];
bool pm_support;
bool ltr_enabled;
};
π¦ Members π¦
okay bestie, here's the full tour, no skipping, we're doing ALL of them π
rxqβ all the RX queue data. every single queue's whole deal lives here β¨rx_poolβ the initial pool ofiwl_rx_mem_bufferfor all the queuesglobal_tableβ table mapping the received VID from hw to rxbrbaβ the allocator for RX replenishing{unnamed_union}β anonymous. mysterious. we don't know her name. π«Άctxt_infoβ context information for FW self initctxt_info_v2β context information for v1 devicesprph_infoβ prph info for self initprph_scratchβ prph scratch for self initimlβ image loader image virtual addressiml_lenβ image loader image sizectxt_info_dma_addrβ dma addr of context informationprph_info_dma_addrβ dma addr of prph infoprph_scratch_dma_addrβ dma addr of prph scratchiml_dma_addrβ image loader image DMA addresstransβ pointer to the generic transport areanapi_devβ the (fake) netdev for NAPI registration. fake it till you make it πict_tblβ ICT table pointerict_tbl_dmaβ ICT table DMA addressict_indexβ current ICT read indexuse_ictβ whether or not ICT (interrupt table) is usedis_downβ indicates the NIC is downopmode_downβ indicates opmode went awaydebug_rfkillβ RF-kill debugging state,-1for unset,0/1for radio enable/disableisr_statsβ interrupt statisticsirq_lockβ lock to synchronize IRQ handlingmutexβ to protectstop_device/start_fw/start_hwinta_maskβ interrupt (INT-A) maskscd_base_addrβ scheduler sram base address in SRAMkwβ keep warm address π₯pnvm_dataβ holds info about pnvm payloads allocated in DRAMreduced_tables_dataβ holds info about power reduced tablse payloads allocated in DRAM (yes, "tablse" β word for word, we don't edit the original's typo, that's the author's child π)txq_memoryβ TXQ allocation arraypci_devβ basic pci-network driver stuffhw_baseβ pci hardware address supportucode_write_completeβ indicates that the ucode has been copied. βsx_stateβ state tracking Sx transitionsucode_write_waitqβ wait queue for uCode loadsx_waitqβ waitqueue for Sx transitionsnum_rx_bufsβ number of RX buffers to allocate/userx_page_orderβ page order for receive buffer sizerx_buf_bytesβ RX buffer (RB) size in bytessupported_dma_maskβ DMA mask to validate the actual address against, will beDMA_BIT_MASK(11)orDMA_BIT_MASK(12)depending on the devicealloc_page_lockβ spinlock for the page allocatoralloc_pageβ allocated page to still use parts ofalloc_page_usedβ how much of the allocated page was already used (bytes)reg_lockβ protect hw register accesscmd_hold_nic_awakeβ indicates NIC is held awake for APMG workaround during commands in flightfw_mon_dataβ fw continuous recording datamsix_entriesβ array of MSI-X entriesmsix_enabledβtrueif managed to enable MSI-Xshared_vec_maskβ the type of causes the shared vector handles (seeiwl_shared_irq_flags).alloc_vecsβ the number of interrupt vectors allocated by the OSdef_irqβ default irq for non rx causesfh_init_maskβ initial unmasked fh causeshw_init_maskβ initial unmasked hw causesfh_maskβ current unmasked fh causeshw_maskβ current unmasked hw causesaffinity_maskβ IRQ affinity mask for each RX queuein_rescanβtrueif we have triggered a device rescanbase_rb_sttsβ base virtual address of receive buffer status for all queuesbase_rb_stts_dmaβ base physical address of receive buffer statusfw_reset_stateβ state of FW reset handshakefw_reset_waitqβ waitqueue for FW reset handshakeimr_statusβ imr dma state machineimr_waitqβ imr wait queue for dma completionrf_nameβ name/version of the CRF, if anytxqsβ transport tx queues data.me_presentβ WiAMT/CSME is detected as present (1), not present (0) or unknown (-1, so can still use it as a boolean safely)me_recheck_wkβ worker to recheck WiAMT/CSME presenceinvalid_tx_cmdβ invalid TX command bufferwait_command_queueβ wait queue for sync commandsdev_cmd_poolβ pool for Tx cmd allocation β for internal use only. The user should useiwl_trans_{alloc,free}_tx_cmd. π no touching, that's an internal-use-only situationdev_cmd_pool_nameβ name for the TX command allocation poolpm_supportβ set totrueinstart_hwif link pm is supportedltr_enabledβ set totrueif the LTR is enabled
also lowkey note: tx_cmd_queue_size is chillin' in the struct up there but the Members list doesn't describe it, so we're not gonna make anything up about it. we respect the mystery π
π₯ SEE ALSO π₯
the whole friend group, fr fr:
- Kernel file
./drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/internal.h struct iwl_rx_mem_buffer(9)struct iwl_rx_transfer_desc(9)struct iwl_rx_completion_desc(9)struct iwl_rx_completion_desc_bz(9)struct iwl_rxq(9)struct iwl_rb_allocator(9)iwl_get_closed_rb_stts(9)enum iwl_fw_mon_dbgfs_state(9)enum iwl_shared_irq_flags(9)enum iwl_image_response_code(9)struct cont_rec(9)enum iwl_pcie_imr_status(9)struct iwl_txq(9)struct iwl_pcie_txqs(9)iwl_txq_inc_wrap(9)iwl_txq_dec_wrap(9)
and that's the whole page bestie, you ate it up π this dropped from ./drivers/net/wireless/intel/i... back in October 2026, and it's titled struct iwl_trans_pcie(9) β go forth and read the source, ily, bye π¦β¨π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms