STRUCT IP30_HEART_REGS(9)

💖 NAME 💖

okay so welcome to the struct ip30_heart_regs(9) page from the Kernel API Manual, bestie ✨ — this is literally the struct that maps IP30 HEART registers 💅

✨ SYNOPSIS ✨

no cap, here’s the whole struct exactly as it is, every field in its little lane 🫶

       struct ip30_heart_regs {
           u64 mode;
           u64 sdram_mode;
           u64 mem_refresh;
           u64 mem_req_arb;
           union {
             u64 q[HEART_MEMORY_BANKS];
             u32 l[HEART_MEMORY_BANKS * 2];
           } mem_cfg;
           u64 fc_mode;
           u64 fc_timer_limit;
           u64 fc_addr[2];
           u64 fc_credit_cnt[2];
           u64 fc_timer[2];
           u64 status;
           u64 bus_err_addr;
           u64 bus_err_misc;
           u64 mem_err_addr;
           u64 mem_err_data;
           u64 piur_acc_err;
           u64 mlan_clock_div;
           u64 mlan_ctrl;
           u64 __pad0[0x01e8];
           u64 undefined;
           u64 __pad1[0x1dff];
           u64 imr[HEART_MAX_CPUS];
           u64 set_isr;
           u64 clear_isr;
           u64 isr;
           u64 imsr;
           u64 cause;
           u64 __pad2[0x1ff7];
           u64 count;
           u64 __pad3[0x1fff];
           u64 compare;
           u64 __pad4[0x1fff];
           u64 trigger;
           u64 __pad5[0x1fff];
           u64 cpuid;
           u64 __pad6[0x1fff];
           u64 sync;
        };

🫶 Members 🫶

okay bestie, every single member, in order, with the lore 👑:

• mode — maps to HEART_MODE; Purpose Unknown, but machine reset gets called from here 👀
• sdram_mode — maps to HEART_SDRAM_MODE; purpose unknown 🦋
• mem_refresh — maps to HEART_MEM_REF; purpose unknown 🌸
• mem_req_arb — maps to HEART_MEM_REQ_ARB; purpose unknown 🎀
• mem_cfg.q — union for 64bit access to HEART_MEMCFG — 4x 64bit registers 💅
• mem_cfg.l — union for 32bit access to HEART_MEMCFG — 8x 32bit registers 💅
• fc_mode — maps to HEART_FC_MODE; Purpose Unknown, possibly for GFX flow control 🌀
• fc_timer_limit — maps to HEART_FC_TIMER_LIMIT; purpose unknown ⏳
• fc_addr — maps to HEART_FC0_ADDR, HEART_FC1_ADDR; purpose unknown 📍
• fc_credit_cnt — maps to HEART_FC0_CR_CNT, HEART_FC1_CR_CNT; purpose unknown 🪙
• fc_timer — maps to HEART_FC0_TIMER, HEART_FC1_TIMER; purpose unknown ⌛
• status — maps to HEART_STATUS; HEART status information 💖
• bus_err_addr — maps to HEART_BERR_ADDR; likely contains addr of recent SIGBUS 😭
• bus_err_misc — maps to HEART_BERR_MISC; purpose unknown 🙈
• mem_err_addr — maps to HEART_MEMERR_ADDR; likely contains addr of recent mem err 💀
• mem_err_data — maps to HEART_MEMERR_DATA; purpose unknown 🍓
• piur_acc_err — maps to HEART_PIUR_ACC_ERR; likely for access err to HEART regs 🚨
• mlan_clock_div — maps to HEART_MLAN_CLK_DIV; MicroLAN clock divider 🕰️
• mlan_ctrl — maps to HEART_MLAN_CTL; MicroLAN control 🎛️
• __pad0 — 0x0f40 bytes of padding -> next HEART register 0x01000 🧚
• undefined — Undefined/diag register, write to it triggers PIUR_ACC_ERR ⚠️
• __pad1 — 0xeff8 bytes of padding -> next HEART register 0x10000 🧚
• imr — HEART_IMR0 to HEART_IMR3 — per-cpu interrupt mask register 🛡️
• set_isr — maps to HEART_SET_ISR; set interrupt status register ✅
• clear_isr — maps to HEART_CLR_ISR; clear interrupt status register 🧹
• isr — maps to HEART_ISR; interrupt status register (read-only) 👀
• imsr — maps to HEART_IMSR; purpose unknown 🤷‍♀️
• cause — maps to HEART_CAUSE; HEART cause information 🔍
• __pad2 — 0xffb8 bytes of padding -> next HEART register 0x20000 🧚
• count — maps to HEART_COUNT; 52-bit counter 🔢
• __pad3 — 0xfff8 bytes of padding -> next HEART register 0x30000 🧚
• compare — maps to HEART_COMPARE; 24-bit compare ⚖️
• __pad4 — 0xfff8 bytes of padding -> next HEART register 0x40000 🧚
• trigger — maps to HEART_TRIGGER; purpose unknown 🎯
• __pad5 — 0xfff8 bytes of padding -> next HEART register 0x50000 🧚
• cpuid — maps to HEART_PRID; contains CPU ID of CPU currently accessing HEART 🪪
• __pad6 — 0xfff8 bytes of padding -> next HEART register 0x60000 🧚
• sync — maps to HEART_SYNC; purpose unknown 🔄

🌸 DESCRIPTION 🌸

HEART is the main system controller ASIC for the IP30 system. It incorporates a memory controller, interrupt status/cause/set/clear management, basic timer with count/compare, and other functionality. For Linux, not all of HEART’s functions are fully understood 😭

Implementation note: All HEART registers are 64bits-wide, but the mem_cfg register only reports correct values if queried in 32bits. Hence the need for a union. Even though mem_cfg.l has 8 array slots, we only ever query up to 4 of those. IP30 has 8 DIMM slots arranged into 4 banks, w/ 2 DIMMs per bank. Each 32bit read accesses one of these banks. Perhaps HEART was designed to address up to 8 banks (16 DIMMs)? We may never know 🤔💭

👑 SEE ALSO 👑

• Kernel file ./arch/mips/include/asm/sgi/heart.h 📖✨

mwah 💋 this page lives in ./arch/mips/include/asm/sgi, dated October 2026, and it’s literally the struct ip30_heart_regs(9) manual. byeee bestie 🫶🌈