STRUCT IONIC_TXQ_DESC(9)

💅 struct ionic_txq_desc(9) — Ethernet Tx queue descriptor format

okay so this is a page from the Kernel API Manual, and it's all about struct ionic_txq_desc — the little blob of bits your NIC reads to know how to yeet a packet out the door. it's giving "the receipt for your packet" energy fr fr 🧾✨

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🌸 SYNOPSIS 🌸

bestie, here's the whole struct, verbatim, no cap:

struct ionic_txq_desc {
    __le64 cmd;
  #define IONIC_TXQ_DESC_OPCODE_MASK              0xf;
  #define IONIC_TXQ_DESC_OPCODE_SHIFT             4;
  #define IONIC_TXQ_DESC_FLAGS_MASK               0xf;
  #define IONIC_TXQ_DESC_FLAGS_SHIFT              0;
  #define IONIC_TXQ_DESC_NSGE_MASK                0xf;
  #define IONIC_TXQ_DESC_NSGE_SHIFT               8;
  #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1);
  #define IONIC_TXQ_DESC_ADDR_SHIFT               12;
  #define IONIC_TXQ_DESC_FLAG_VLAN                0x1;
  #define IONIC_TXQ_DESC_FLAG_ENCAP               0x2;
  #define IONIC_TXQ_DESC_FLAG_CSUM_L3             0x4;
  #define IONIC_TXQ_DESC_FLAG_CSUM_L4             0x8;
  #define IONIC_TXQ_DESC_FLAG_TSO_SOT             0x4;
  #define IONIC_TXQ_DESC_FLAG_TSO_EOT             0x8;
    __le16 len;
    union {
      __le16 vlan_tci;
      __le16 hword0;
    };
    union {
      __le16 csum_start;
      __le16 hdr_len;
      __le16 hword1;
    };
    union {
      __le16 csum_offset;
      __le16 mss;
      __le16 hword2;
    };
 };

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🎀 Members 🎀

like, every field, one at a time, no skipping 🙅‍♀️

• cmd — the Tx operation itself, see IONIC_TXQ_DESC_OPCODE_* (there's a whole opcode menu below, keep scrolling bestie 💖)
• len — the length of the first data buffer, in bytes. first one only, she's special.
• {unnamed_union} — anonymous. yes literally just an anonymous union, we love a mystery ✨
• vlan_tci — the VLAN tag to insert into the packet (only if the V-bit asked for it). includes the .1p and .1q tags.
• hword0 — half word padding. filler queen 👑
• {unnamed_union} — anonymous (again 💀)
• csum_start — offset from the packet to the first byte checked in the L4 checksum.
• hdr_len — the length of the packet headers, and it includes the encapsulating outer header if that applies. this one is only valid for the opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and IONIC_TXQ_DESC_OPCODE_TSO, and it should be set to zero for all other modes. so like, don't leave it lying around. for IONIC_TXQ_DESC_OPCODE_CALC_CSUM, hdr_len is the length of headers up to the inner-most L4 header. for IONIC_TXQ_DESC_OPCODE_TSO, hdr_len goes up to the inner-most L4 payload, so it's inclusive of the inner-most L4 header. subtle but important, iykyk.
• hword1 — half word padding 🫶
• {unnamed_union} — anonymous, the third one, they're multiplying 😭
• csum_offset — offset from csum_start to the L4 checksum field.
• mss — the desired MSS value for TSO. only applicable for IONIC_TXQ_DESC_OPCODE_TSO, so mind your business otherwise.
• hword2 — half word padding, last one, we made it 🌈

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💜 Description 💜

so the cmd field has an opcode, and the opcode decides the whole personality of the descriptor. here's the roster:

⭐ IONIC_TXQ_DESC_OPCODE_CSUM_NONE

Non-offload send, periodt. no segmentation, no fragmentation, no checksum calc/insertion — the device does none of it. the packet was already prepped by the software stack and needs zero further manipulation from the device. she's just here to deliver 📦

⭐ IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL

offload that 16-bit L4 checksum calculation/insertion, bestie. the device calculates the L4 checksum value and inserts the result in the packet's L4 header checksum field. the L4 checksum is calculated starting at csum_start bytes into the packet, all the way to the end of the packet. the checksum insertion position is given in csum_offset, which is the offset from csum_start to the checksum field in the L4 header.

this feature is only applicable to protocols like TCP, UDP and ICMP — the ones where a standard (i.e. the 'IP-style' checksum) one's complement 16-bit checksum is used, seeded with an IP pseudo-header to start the calculation. software will preload the L4 checksum field with the IP pseudo-header checksum. teamwork 💅

for tunnel encapsulation, csum_start and csum_offset refer to the inner L4 header. supported tunnel encapsulations are: IPIP, GRE, and UDP. if the encap is clear, no further processing by the device is required — software will calculate the outer header checksums. if the encap is set, the device will offload the outer header checksums using LCO (local checksum offload) (see Documentation/networking/checksum-offloads.rst for more info). yes go read the docs, i'll wait 🍓

⭐ IONIC_TXQ_DESC_OPCODE_CSUM_HW

offload 16-bit checksum computation to hardware. if csum_l3 is set then the packet's L3 checksum is updated. similarly, if csum_l4 is set the L4 checksum is updated. and if encap is set then encap header checksums are also updated. everybody gets a glow-up ✨

⭐ IONIC_TXQ_DESC_OPCODE_TSO

device performs TCP segmentation offload (TSO). hdr_len is the number of bytes to the end of the TCP header (the offset to the TCP payload). mss is the desired MSS, the TCP payload length for each segment. the device will calculate/insert IP (IPv4 only) and TCP checksums for each segment. in the first data buffer containing the header template, the driver will set the IPv4 checksum to 0 and preload the TCP checksum with the IP pseudo header calculated with IP length = 0.

supported tunnel encapsulations are IPIP, layer-3 GRE, and UDP. hdr_len includes both outer and inner headers. the driver will set the IPv4 checksum to zero and preload the TCP checksum with IP pseudo header on the inner header.

TCP ECN offload is supported 🎉 the device will set the CWR flag in the first segment if CWR is set in the template header, and clear CWR in remaining segments.

👑 and now the flags, get comfy:

• vlan: insert an L2 VLAN header using vlan_tci
• encap: calculate encap header checksum
• csum_l3: compute L3 header checksum
• csum_l4: compute L4 header checksum
• tso_sot: TSO start
• tso_eot: TSO end
• num_sg_elems: number of scatter-gather elements in SG descriptor
• addr: first data buffer's DMA address (subsequent data buffers are on txq_sg_desc)

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🦋 SEE ALSO 🦋

the whole squad, the entire friend group chat, from the kernel file ./drivers/net/ethernet/pensando/ionic/ionic_if.h — every single one, i'm not skipping anybody:

struct ionic_admin_cmd(9), struct ionic_admin_comp(9), struct ionic_nop_cmd(9),
struct ionic_nop_comp(9), struct ionic_dev_init_cmd(9), struct
ionic_dev_init_comp(9), struct ionic_dev_reset_cmd(9), struct
ionic_dev_reset_comp(9), struct ionic_dev_identify_cmd(9), struct
ionic_dev_identify_comp(9), union ionic_drv_identity(9), enum
ionic_dev_capability(9), union ionic_dev_identity(9), struct
ionic_lif_identify_cmd(9), struct ionic_lif_identify_comp(9), enum
ionic_lif_capability(9), enum ionic_logical_qtype(9), enum
ionic_q_feature(9), enum ionic_rxq_feature(9), enum
ionic_txq_feature(9), enum ionic_hwstamp_bits(9), struct
ionic_lif_logical_qtype(9), enum ionic_lif_state(9), union
ionic_lif_config(9), enum ionic_lif_rdma_cap_stats(9), union
ionic_lif_identity(9), struct ionic_lif_init_cmd(9), struct
ionic_lif_init_comp(9), struct ionic_q_identify_cmd(9), struct
ionic_q_identify_comp(9), union ionic_q_identity(9), struct
ionic_q_init_cmd(9), struct ionic_q_init_comp(9), struct
ionic_txq_sg_elem(9), struct ionic_txq_sg_desc(9), struct
ionic_txq_comp(9), struct ionic_rxq_desc(9), struct
ionic_rxq_sg_elem(9), struct ionic_rxq_sg_desc(9), struct
ionic_rxq_comp(9), enum ionic_pkt_class(9), struct
ionic_q_control_cmd(9), enum ionic_phy_type(9), enum
ionic_xcvr_state(9), enum ionic_port_type(9), enum
ionic_port_admin_state(9), enum ionic_port_oper_status(9), enum
ionic_port_fec_type(9), enum ionic_port_pause_type(9), enum
ionic_port_loopback_mode(9), struct ionic_xcvr_status(9), union
ionic_port_config(9), struct ionic_port_status(9), struct
ionic_port_identify_cmd(9), struct ionic_port_identify_comp(9), struct
ionic_port_init_cmd(9), struct ionic_port_init_comp(9), struct
ionic_port_reset_cmd(9), struct ionic_port_reset_comp(9), enum
ionic_stats_ctl_cmd(9), enum ionic_txstamp_mode(9), enum
ionic_port_attr(9), struct ionic_port_setattr_cmd(9), struct
ionic_port_setattr_comp(9), struct ionic_port_getattr_cmd(9), struct
ionic_port_getattr_comp(9), struct ionic_lif_status(9), struct
ionic_lif_reset_cmd(9), enum ionic_dev_attr(9), struct
ionic_dev_setattr_cmd(9), struct ionic_dev_setattr_comp(9), struct
ionic_dev_getattr_cmd(9), struct ionic_dev_getattr_comp(9), enum
ionic_lif_attr(9), struct ionic_lif_setattr_cmd(9), struct
ionic_lif_setattr_comp(9), struct ionic_lif_getattr_cmd(9), struct
ionic_lif_getattr_comp(9), struct ionic_lif_setphc_cmd(9), struct
ionic_rx_mode_set_cmd(9), struct ionic_rx_filter_add_cmd(9), struct
ionic_rx_filter_add_comp(9), struct ionic_rx_filter_del_cmd(9), enum
ionic_vf_link_status(9), struct ionic_vf_setattr_cmd(9), struct
ionic_vf_getattr_cmd(9), struct ionic_vf_ctrl_cmd(9), struct
ionic_vf_ctrl_comp(9), struct ionic_discover_cmb_cmd(9), struct
ionic_discover_cmb_comp(9), union ionic_cmb_region(9), union
ionic_discover_cmb_identity(9), struct ionic_qos_identify_cmd(9), struct
ionic_qos_identify_comp(9), enum ionic_qos_class_type(9), enum
ionic_qos_sched_type(9), union ionic_qos_config(9), union
ionic_qos_identity(9), struct ionic_qos_init_cmd(9), struct
ionic_qos_reset_cmd(9), struct ionic_qos_clear_stats_cmd(9), struct
ionic_fw_download_cmd(9), enum ionic_fw_control_oper(9), struct
ionic_fw_control_cmd(9), struct ionic_fw_control_comp(9), struct
ionic_rdma_reset_cmd(9), struct ionic_rdma_queue_cmd(9), struct
ionic_notifyq_event(9), struct ionic_link_change_event(9), struct
ionic_reset_event(9), struct ionic_heartbeat_event(9), struct
ionic_log_event(9), struct ionic_xcvr_event(9), union
ionic_port_identity(9), struct ionic_port_info(9), struct
ionic_lif_info(9), struct ionic_hwstamp_regs(9), union
ionic_dev_info_regs(9), union ionic_dev_cmd_regs(9), union
ionic_dev_regs(9), struct ionic_doorbell(9)

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ngl that's a lot of see-also, but that's the friend group and we respect it 🫶

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that's the whole page bestie!! 💖 sourced from ./drivers/net/ethernet/pensand… (yes it's truncated like that, don't come for me), October 2026 edition — go forth and describe your Tx queues, you absolute icon 👑✨