STRUCT IONIC_Q_INIT_CMD(9)

💅 struct ionic_q_init_cmd(9) — the queue init command, bestie

okay so first things first: this is a page from the Kernel API Manual, section 9, and the star of the show is struct ionic_q_init_cmd — literally the queue init command. it's the lil struct you hand to the NIC when you want a fresh queue to exist. main character energy, no cap.

✨ NAME ✨

struct ionic_q_init_cmd - Queue init command

🎀 SYNOPSIS 🎀

here's the whole struct, verbatim, don't touch the formatting bestie it's load-bearing:

struct ionic_q_init_cmd {
    u8 opcode;
    u8 rsvd;
    __le16 lif_index;
    u8 type;
    u8 ver;
    u8 rsvd1[2];
    __le32 index;
    __le16 pid;
    __le16 intr_index;
    __le16 flags;
  #define IONIC_QINIT_F_IRQ       0x01    ;
  #define IONIC_QINIT_F_ENA       0x02    ;
  #define IONIC_QINIT_F_SG        0x04    ;
  #define IONIC_QINIT_F_EQ        0x08    ;
  #define IONIC_QINIT_F_CMB       0x10    ;
  #define IONIC_QINIT_F_DEBUG     0x80    ;
    u8 cos;
    u8 ring_size;
    __le64 ring_base;
    __le64 cq_ring_base;
    __le64 sg_ring_base;
    u8 rsvd2[12];
    __le64 features;
 };

look at all those reserved bytes just vibing 🌸 they're reserved, we leave them alone, we do not perceive them.

🦋 Members 🦋

okay now the field-by-field tour, buckle up 🎢

opcode — opcode. that's it, that's the description. iconic minimalism honestly 💅
rsvd — reserved byte(s) 🫶 hands off
lif_index — LIF index
type — Logical queue type
ver — Queue type version
rsvd1 — reserved byte(s) (yes, a second helping, there's also rsvd2 later, they're multiplying)
index — (LIF, qtype) relative admin queue index
pid — Process ID
intr_index — Interrupt control register index, or Event queue index
flags — the bitmask situation. here's what each define means:
- IRQ (0x01) — Interrupt requested on completion
- ENA (0x02) — Enable the queue. If ENA=0 the queue is initialized but remains disabled, to be later enabled with the Queue Enable command. If ENA=1, then queue is initialized and then enabled.
- SG (0x04) — Enable Scatter-Gather on the queue.
- EQ (0x08) — Enable the Event Queue
- and heads up: IONIC_QINIT_F_CMB (0x10) and IONIC_QINIT_F_DEBUG (0x80) are defined right there in the struct but the page doesn't spell them out, so bestie I'm not gonna invent lore for them fr fr 🙈

ngl the source page smushes the entire ring-size explainer into this flags entry (doc glitch energy 😭). I'm putting those sentences where they belong, down at ring_size, but it's the exact same words, promise.

cos — Class of service for this queue
ring_size — Queue ring size, encoded as a log2(size). here's the full tea: the ring size is expressed in number of descs. the actual ring size is (1 << ring_size). for example, to select a ring size of 64 descriptors write ring_size = 6. the minimum ring_size value is 2 for a ring size of 4 descriptors. the maximum ring_size value is 16 for a ring size of 64k descriptors. values of ring_size <2 and >16 are reserved ⭐
ring_base — Queue ring base address
cq_ring_base — Completion queue ring base address
sg_ring_base — Scatter/Gather ring base address
rsvd2 — reserved byte(s) 🧚 the third reserved field, we stan a consistent bit of housekeeping
features — Mask of queue features to enable, if not in the flags above.

🌸 SEE ALSO 🌸

the source for all of this lives in the kernel file ./drivers/net/ethernet/pensando/ionic/ionic_if.h — and it is a whole friend group, ok, there are SO many. all of them, in order, no skips:

struct ionic_admin_cmd(9), struct ionic_admin_comp(9), struct ionic_nop_cmd(9), struct ionic_nop_comp(9), struct ionic_dev_init_cmd(9), struct ionic_dev_init_comp(9), struct ionic_dev_reset_cmd(9), struct ionic_dev_reset_comp(9), struct ionic_dev_identify_cmd(9), struct ionic_dev_identify_comp(9), union ionic_drv_identity(9), enum ionic_dev_capability(9), union ionic_dev_identity(9), struct ionic_lif_identify_cmd(9), struct ionic_lif_identify_comp(9), enum ionic_lif_capability(9), enum ionic_logical_qtype(9), enum ionic_q_feature(9), enum ionic_rxq_feature(9), enum ionic_txq_feature(9), enum ionic_hwstamp_bits(9), struct ionic_lif_logical_qtype(9), enum ionic_lif_state(9), union ionic_lif_config(9), enum ionic_lif_rdma_cap_stats(9), union ionic_lif_identity(9), struct ionic_lif_init_cmd(9), struct ionic_lif_init_comp(9), struct ionic_q_identify_cmd(9), struct ionic_q_identify_comp(9), union ionic_q_identity(9), struct ionic_q_init_comp(9), struct ionic_txq_desc(9), struct ionic_txq_sg_elem(9), struct ionic_txq_sg_desc(9), struct ionic_txq_comp(9), struct ionic_rxq_desc(9), struct ionic_rxq_sg_elem(9), struct ionic_rxq_sg_desc(9), struct ionic_rxq_comp(9), enum ionic_pkt_class(9), struct ionic_q_control_cmd(9),

enum ionic_phy_type(9), enum ionic_xcvr_state(9), enum ionic_port_type(9), enum ionic_port_admin_state(9), enum ionic_port_oper_status(9), enum ionic_port_fec_type(9), enum ionic_port_pause_type(9), enum ionic_port_loopback_mode(9), struct ionic_xcvr_status(9), union ionic_port_config(9), struct ionic_port_status(9), struct ionic_port_identify_cmd(9), struct ionic_port_identify_comp(9), struct ionic_port_init_cmd(9), struct ionic_port_init_comp(9), struct ionic_port_reset_cmd(9), struct ionic_port_reset_comp(9), enum ionic_stats_ctl_cmd(9), enum ionic_txstamp_mode(9), enum ionic_port_attr(9), struct ionic_port_setattr_cmd(9), struct ionic_port_setattr_comp(9), struct ionic_port_getattr_cmd(9), struct ionic_port_getattr_comp(9), struct ionic_lif_status(9), struct ionic_lif_reset_cmd(9), enum ionic_dev_attr(9), struct ionic_dev_setattr_cmd(9), struct ionic_dev_setattr_comp(9), struct ionic_dev_getattr_cmd(9), struct ionic_dev_getattr_comp(9), enum ionic_lif_attr(9), struct ionic_lif_setattr_cmd(9), struct ionic_lif_setattr_comp(9), struct ionic_lif_getattr_cmd(9), struct ionic_lif_getattr_comp(9), struct ionic_lif_setphc_cmd(9),

struct ionic_rx_mode_set_cmd(9), struct ionic_rx_filter_add_cmd(9), struct ionic_rx_filter_add_comp(9), struct ionic_rx_filter_del_cmd(9), enum ionic_vf_link_status(9), struct ionic_vf_setattr_cmd(9), struct ionic_vf_getattr_cmd(9), struct ionic_vf_ctrl_cmd(9), struct ionic_vf_ctrl_comp(9), struct ionic_discover_cmb_cmd(9), struct ionic_discover_cmb_comp(9), union ionic_cmb_region(9), union ionic_discover_cmb_identity(9), struct ionic_qos_identify_cmd(9), struct ionic_qos_identify_comp(9), enum ionic_qos_class_type(9), enum ionic_qos_sched_type(9), union ionic_qos_config(9), union ionic_qos_identity(9), struct ionic_qos_init_cmd(9), struct ionic_qos_reset_cmd(9), struct ionic_qos_clear_stats_cmd(9), struct ionic_fw_download_cmd(9), enum ionic_fw_control_oper(9), struct ionic_fw_control_cmd(9), struct ionic_fw_control_comp(9), struct ionic_rdma_reset_cmd(9), struct ionic_rdma_queue_cmd(9),

struct ionic_notifyq_event(9), struct ionic_link_change_event(9), struct ionic_reset_event(9), struct ionic_heartbeat_event(9), struct ionic_log_event(9), struct ionic_xcvr_event(9), union ionic_port_identity(9), struct ionic_port_info(9), struct ionic_lif_info(9), struct ionic_hwstamp_regs(9), union ionic_dev_info_regs(9), union ionic_dev_cmd_regs(9), union ionic_dev_regs(9), struct ionic_doorbell(9)

like I said. a whole friend group. 💀

lowkey reminder: rsvd, rsvd1 and rsvd2 are reserved byte(s) — you do not write to them, you do not read meaning into them, you leave them exactly as the hardware expects. that's the vibe check. ✨

that's the whole page bestie, go init some queues 🦋

sign-off szn: this page came from ./drivers/net/ethernet/pensand... and it's dated October 2026 — so yeah, it's from the future, we're just built different 💜🎀 see you in the next manpage, mwah 💅

📦 where this page comes from

nixpkgs unstable: linux-manual 7.3.1
💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on 2026-11-04: a language model's rewrite of the original, under its terms