STRUCT INTEL_COMMUNITY(9)

💖 struct intel_community(9) — like, the whole vibe of an Intel pin community 💖

okay so bestie, welcome to the struct intel_community(9) page from the Kernel API Manual ✨ this is the little struct that describes one Intel pin community, and honestly? it's giving "lowkey load-bearing" 🫶

🌸 SYNOPSIS 🌸

struct intel_community {
    unsigned int barno;
    unsigned int padown_offset;
    unsigned int padcfglock_offset;
    unsigned int hostown_offset;
    unsigned int is_offset;
    unsigned int ie_offset;
    unsigned int features;
    unsigned int pin_base;
    size_t npins;
    unsigned int gpp_size;
    unsigned int gpp_num_padown_regs;
    const struct intel_padgroup *gpps;
    size_t ngpps;
    const unsigned int *pad_map;
    unsigned short nirqs;
    unsigned short acpi_space_id;
    void __iomem *regs;
    void __iomem *pad_regs;
 };

✨ Members ✨

• barno — the MMIO BAR number where this community's registers live 🏠 that's the house, fr fr.
• padown_offset — register offset of the PAD_OWN register from regs. if it's 0, there's no owner support at all — no PAD_OWN era, we don't know her 💀
• padcfglock_offset — register offset of PADCFGLOCK from regs. if it's 0 then locking is literally not supported 🔒😭
• hostown_offset — register offset of HOSTSW_OWN from regs. if it's 0, the driver assumes the host owns the pin (rather than ACPI) — so like, host said "mine" 💅
• is_offset — register offset of GPI_IS from regs ✨
• ie_offset — register offset of GPI_IE from regs ✨
• features — extra features the hardware has going on 🎀 additional features supported by the hardware, no cap.
• pin_base — the starting pin of the pins in this community 🌱 where the pin party begins.
• npins — number of pins in this community 🔢
• gpp_size — maximum number of pads in each group (think PADCFGLOCK, HOSTSW_OWN, GPI_IS, GPI_IE). used when gpps is NULL 👀
• gpp_num_padown_regs — number of pad registers each pad group consumes at minimum. also used when gpps is NULL 🫶
• gpps — pad groups, for when the controller has variable size pad groups 🦋 (the "it's complicated" option).
• ngpps — number of pad groups in this community 🔢✨
• pad_map — optional non-linear mapping of the pads 🗺️ optional, bestie, so don't come for her if she's NULL.
• nirqs — optional total number of IRQs this community can generate ⚡ optional again!
• acpi_space_id — optional address space ID for the ACPI OpRegion handler 🏷️ optional x3, she's flexible.
• regs — community specific common registers 🔧 reserved for core driver — hands off, that's core driver's business 🙈
• pad_regs — community specific pad registers 🔧 also reserved for core driver, same energy.

🌈 Description 🌈

okay so here's the tea ☕ in the older Intel GPIO host controllers this driver supports, every pad group is the same size (except the last one, she's special 🎀). in that case the driver can literally just fill in the gpp_size and gpp_num_padown_regs fields and let the core driver handle the rest. easy, iconic, minimal effort, we love a low-effort slay ✨

but in the newer Intel GPIO host controllers, each pad group is of variable size 😭 so the client driver can pass custom gpps and ngpps instead. it's giving "we do things differently now" 💅 periodt.

👑 SEE ALSO 👑

• Kernel file ./drivers/pinctrl/intel/pinctrl-intel.h struct intel_pingroup(9), struct intel_function(9), struct intel_padgroup(9), enum (anonymous)(9), PIN_GROUP(9), struct intel_pinctrl_soc_data(9), struct intel_pinctrl_context(9), struct intel_pinctrl(9)

like, go read those too, they're all in the same friend group fr fr 🫶✨

k bye bestie!! 🦋 this page came from ./drivers/pinctrl/intel, dated October 2026, and it's part of the Kernel API Manual 💖 go forth and pin responsibly 💅✨