STRUCT INGENIC_CGU_PLL_INFO(9)

hii bestie!! welcome to struct ingenic_cgu_pll_info(9) in the Kernel API Manual — this is the little struct that holds information about a PLL, and we're gonna read it like a group-chat receipt 💖✨

✨ NAME ✨

struct ingenic_cgu_pll_info — information about a PLL. That's the name line, and honestly it ate: it's literally the struct for PLL info, periodt 💅

🦋 SYNOPSIS 🦋

here's the struct in all its glory, copied exactly because we do NOT mess with code, bestie:

       struct ingenic_cgu_pll_info {
           unsigned reg;
           unsigned rate_multiplier;
           const s8 *od_encoding;
           u8 m_shift, m_bits, m_offset;
           u8 n_shift, n_bits, n_offset;
           u8 od_shift, od_bits, od_max;
           unsigned bypass_reg;
           s8 bypass_bit;
           s8 enable_bit;
           s8 stable_bit;
           void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info,
       unsigned long rate, unsigned long parent_rate, unsigned int *m, unsigned
       int *n, unsigned int *od);
           void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info,
       unsigned long rate, unsigned long parent_rate);
        };

quick note, bestie: calc_m_n_od is right there in the struct, but the original Members section doesn't give it a separate description — so I'm not inventing one 🙈

🎀 Members 🎀

okay bestie, member-by-member, no gatekeeping:

• reg — the offset of the PLL's control register within the CGU
• rate_multiplier — the multiplier needed by PLL rate calculation
• od_encoding — a pointer to an array mapping post-VCO divider values to their encoded values in the PLL control register, or -1 for unsupported values
• m_shift — the number of bits to shift the multiplier value by (ie. the index of the lowest bit of the multiplier value in the PLL's control register)
• m_bits — the size of the multiplier field in bits
• m_offset — the multiplier value which encodes to 0 in the PLL's control register
• n_shift — the number of bits to shift the divider value by (ie. the index of the lowest bit of the divider value in the PLL's control register)
• n_bits — the size of the divider field in bits
• n_offset — the divider value which encodes to 0 in the PLL's control register
• od_shift — the number of bits to shift the post-VCO divider value by (ie. the index of the lowest bit of the post-VCO divider value in the PLL's control register)
• od_bits — the size of the post-VCO divider field in bits, or 0 if no OD field exists (then the OD is fixed to 1)
• od_max — the maximum post-VCO divider value
• bypass_reg — the offset of the bypass control register within the CGU
• bypass_bit — the index of the bypass bit in the PLL control register, or -1 if there is no bypass bit
• enable_bit — the index of the enable bit in the PLL control register, or -1 if there is no enable bit (ie, the PLL is always on)
• stable_bit — the index of the stable bit in the PLL control register, or -1 if there is no stable bit
• set_rate_hook — hook called immediately after updating the CGU register, before releasing the spinlock

🔎 SEE ALSO 🔎

peep the kernel file ./drivers/clk/ingenic/cgu.h, and then these icons too:

• struct ingenic_cgu_mux_info(9)
• struct ingenic_cgu_div_info(9)
• struct ingenic_cgu_fixdiv_info(9)
• struct ingenic_cgu_gate_info(9)
• struct ingenic_cgu_custom_info(9)
• struct ingenic_cgu_clk_info(9)
• struct ingenic_cgu(9)
• struct ingenic_clk(9)
• ingenic_cgu_new(9)
• ingenic_cgu_register_clocks(9)

okay that's the page, bestie!! mwah 💋 source/version: ./drivers/clk/ingenic; date: October 2026; manual name: struct ingenic_cgu_pll_info(9). bye, go make your PLL info cute ✨🫶