STRUCT GAUDI_DEVICE(9)

🦋 NAME 🦋

okay so this is the struct gaudi_device(9) page from the Kernel API Manual, and it's literally the ASIC specific manage structure, bestie. it's giving "device-management main character struct" energy 💅✨

🌸 SYNOPSIS 🌸

struct gaudi_device {
    int (*cpucp_info_get)(struct hl_device *hdev);
    spinlock_t hw_queues_lock;
    struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE];
    struct gaudi_collective_properties collective_props;
    u64 hbm_bar_cur_addr;
    u32 events[GAUDI_EVENT_SIZE];
    u32 events_stat[GAUDI_EVENT_SIZE];
    u32 events_stat_aggregate[GAUDI_EVENT_SIZE];
    u32 hw_cap_initialized;
    u8 mmu_cache_inv_pi;
};

🫶 Members 🫶

• cpucp_info_get — this function pointer gets information on the device from CPU-CP. yep, it's literally the "ask CPU-CP for the device tea" hook, no cap ☕✨
• hw_queues_lock — protects the H/W queues from concurrent access. it's the bouncer for the hardware queue line, keeping everything from crashing the party at once 💅🔥
• internal_qmans — Internal QMANs information. The array size is larger than the actual number of internal queues because they are not in consecutive order. lowkey crucial: do not assume they're packed back-to-back, bestie 🌀

quick sidebar: collective_props is in the struct too, as struct gaudi_collective_properties collective_props; — but this page doesn't give it its own separate member blurb, so I'm not inventing one 🫶

• hbm_bar_cur_addr — current address of HBM PCI bar. literally the current address of the HBM PCI bar, periodt 📍
• events — array that holds all event id's. yes, all the event id's, with that apostrophe exactly how the page says it 🎀
• events_stat — array that holds histogram of all received events. it's the received-events histogram, iykyk 📊
• events_stat_aggregate — same as events_stat but doesn't get cleared on reset. so reset does not wipe this one — that's the whole point, bestie 💀✨
• hw_cap_initialized — This field contains a bit per H/W engine. When that engine is initialized, that bit is set by the driver to signal we can use this engine in later code paths. Each bit is cleared upon reset of its corresponding H/W engine. it's the driver's little "this engine is ready" checkbox grid, and reset unchecks the matching box 👑🔥
• mmu_cache_inv_pi — PI for MMU cache invalidation flow. The H/W expects an 8-bit value so use u8. literally the hardware wants 8 bits, so u8 it is — no overthinking 🧚💜

🌈 SEE ALSO 🌈

• Kernel file ./drivers/accel/habanalabs/gaudi/gaudiP.h struct gaudi_collective_properties(9), struct gaudi_internal_qman_info(9)

k that's the whole page, bestie 💖 source/version is ./drivers/accel/habanalabs/gaudi, the date is October 2026, and the manual tag is struct gaudi_device(9). bye fr fr, go read the header 🌸🦋