STRUCT FSL_SPDIF_PRIV(9)
π struct fsl_spdif_priv(9) β the Kernel API Manual, but make it make sense π
okay so bestie, we're in the kernel API manual today (the 9 is giving "section nine, driver-adjacent, very serious business") and the star of the show is struct fsl_spdif_priv, aka the Freescale SPDIF private data. it's the little backstage dressing room where the SPDIF driver keeps all its stuff. no cap, every field is load-bearing. let's go π
β¨ SYNOPSIS β¨
here's the whole struct, exactly as it lives, don't touch nothin':
struct fsl_spdif_priv {
const struct fsl_spdif_soc_data *soc;
struct spdif_mixer_control fsl_spdif_control;
struct snd_soc_dai_driver cpu_dai_drv;
struct snd_card *snd_card;
struct snd_kcontrol *rxrate_kcontrol;
struct platform_device *pdev;
struct regmap *regmap;
bool dpll_locked;
u32 txrate[SPDIF_TXRATE_MAX];
u8 txclk_df[SPDIF_TXRATE_MAX];
u16 sysclk_df[SPDIF_TXRATE_MAX];
u8 txclk_src[SPDIF_TXRATE_MAX];
u8 rxclk_src;
struct clk *txclk[STC_TXCLK_SRC_MAX];
struct clk *rxclk;
struct clk *coreclk;
struct clk *sysclk;
struct clk *spbaclk;
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct snd_dmaengine_dai_dma_data dma_params_rx;
u32 regcache_srpc;
bool bypass;
struct clk *pll8k_clk;
struct clk *pll11k_clk;
};
lowkey a whole vibe. π¦
π«Ά Members π«Ά
every single field, and what it's actually doing here (iykyk):
socβ SPDIF soc data. the "which SoC are we even on" answer key πΊοΈfsl_spdif_controlβ SPDIF control data. the control-y bit.cpu_dai_drvβ cpu dai driver. the DAI driver, main character energy πsnd_cardβ sound card pointer. yes, the sound card.rxrate_kcontrolβ kcontrol for RX Sample Rate. the knob for capture rate, literally.pdevβ platform device pointer.regmapβ regmap handler. how we talk to registers, slay.dpll_lockedβ dpll lock flag. is the DPLL locked? bool says maybe, this says yes/no πtxrateβ the best rates for playback. array of them, sizedSPDIF_TXRATE_MAXπ₯txclk_dfβSTC_TXCLK_DFdividers value for playback.sysclk_dfβSTC_SYSCLK_DFdividers value for playback.txclk_srcβSTC_TXCLK_SRCvalues for playback.rxclk_srcβSRPC_CLKSRC_SELvalues for capture.txclkβ tx clock sources for playback. it's an array,STC_TXCLK_SRC_MAXof them β°rxclkβ rx clock sources for capture.coreclkβ core clock for register access via DMA.sysclkβ system clock for rx clock rate measurement.spbaclkβ SPBA clock (optional, depending on SoC design). emphasis on optional, don't come for her πdma_params_txβ DMA parameters for transmit channel.dma_params_rxβ DMA parameters for receive channel.regcache_srpcβ regcache for SRPC. yes bestie, we cache the SRPC.bypassβ status of bypass input to output. the direct line, no detours π¦pll8k_clkβ PLL clock for the rate of multiply of 8kHz.pll11k_clkβ PLL clock for the rate of multiply of 11kHz.
π SEE ALSO π
- Kernel file
./sound/soc/fsl/fsl_spdif.cβ where the actual code lives, go read it fr fr π struct fsl_spdif_soc_data(9)β her sibling, also iconic β¨
not me writing a whole manpage and then reminding you to actually read ./sound/soc/fsl/fsl_spdif.c β but like, do it. the struct is only half the story π
and that's the page, bestie π sign-off time: this one comes from ./sound/soc/fsl, dated October 2026, and it's the struct fsl_spdif_priv(9) entry in the Kernel API Manual. periodt. ππΈ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms