STRUCT FSL_SPDIF_PRIV(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– struct fsl_spdif_priv(9) β€” the Kernel API Manual, but make it make sense πŸ’–

okay so bestie, we're in the kernel API manual today (the 9 is giving "section nine, driver-adjacent, very serious business") and the star of the show is struct fsl_spdif_priv, aka the Freescale SPDIF private data. it's the little backstage dressing room where the SPDIF driver keeps all its stuff. no cap, every field is load-bearing. let's go πŸŽ€


✨ SYNOPSIS ✨

here's the whole struct, exactly as it lives, don't touch nothin':

struct fsl_spdif_priv {
    const struct fsl_spdif_soc_data *soc;
    struct spdif_mixer_control fsl_spdif_control;
    struct snd_soc_dai_driver cpu_dai_drv;
    struct snd_card *snd_card;
    struct snd_kcontrol *rxrate_kcontrol;
    struct platform_device *pdev;
    struct regmap *regmap;
    bool dpll_locked;
    u32 txrate[SPDIF_TXRATE_MAX];
    u8 txclk_df[SPDIF_TXRATE_MAX];
    u16 sysclk_df[SPDIF_TXRATE_MAX];
    u8 txclk_src[SPDIF_TXRATE_MAX];
    u8 rxclk_src;
    struct clk *txclk[STC_TXCLK_SRC_MAX];
    struct clk *rxclk;
    struct clk *coreclk;
    struct clk *sysclk;
    struct clk *spbaclk;
    struct snd_dmaengine_dai_dma_data dma_params_tx;
    struct snd_dmaengine_dai_dma_data dma_params_rx;
    u32 regcache_srpc;
    bool bypass;
    struct clk *pll8k_clk;
    struct clk *pll11k_clk;
};

lowkey a whole vibe. πŸ¦‹


🫢 Members 🫢

every single field, and what it's actually doing here (iykyk):

  • soc β€” SPDIF soc data. the "which SoC are we even on" answer key πŸ—ΊοΈ
  • fsl_spdif_control β€” SPDIF control data. the control-y bit.
  • cpu_dai_drv β€” cpu dai driver. the DAI driver, main character energy πŸ‘‘
  • snd_card β€” sound card pointer. yes, the sound card.
  • rxrate_kcontrol β€” kcontrol for RX Sample Rate. the knob for capture rate, literally.
  • pdev β€” platform device pointer.
  • regmap β€” regmap handler. how we talk to registers, slay.
  • dpll_locked β€” dpll lock flag. is the DPLL locked? bool says maybe, this says yes/no πŸ’…
  • txrate β€” the best rates for playback. array of them, sized SPDIF_TXRATE_MAX πŸ”₯
  • txclk_df β€” STC_TXCLK_DF dividers value for playback.
  • sysclk_df β€” STC_SYSCLK_DF dividers value for playback.
  • txclk_src β€” STC_TXCLK_SRC values for playback.
  • rxclk_src β€” SRPC_CLKSRC_SEL values for capture.
  • txclk β€” tx clock sources for playback. it's an array, STC_TXCLK_SRC_MAX of them ⏰
  • rxclk β€” rx clock sources for capture.
  • coreclk β€” core clock for register access via DMA.
  • sysclk β€” system clock for rx clock rate measurement.
  • spbaclk β€” SPBA clock (optional, depending on SoC design). emphasis on optional, don't come for her πŸ™ˆ
  • dma_params_tx β€” DMA parameters for transmit channel.
  • dma_params_rx β€” DMA parameters for receive channel.
  • regcache_srpc β€” regcache for SRPC. yes bestie, we cache the SRPC.
  • bypass β€” status of bypass input to output. the direct line, no detours 🚦
  • pll8k_clk β€” PLL clock for the rate of multiply of 8kHz.
  • pll11k_clk β€” PLL clock for the rate of multiply of 11kHz.

🌈 SEE ALSO 🌈

  • Kernel file ./sound/soc/fsl/fsl_spdif.c β€” where the actual code lives, go read it fr fr πŸ“–
  • struct fsl_spdif_soc_data(9) β€” her sibling, also iconic ✨

not me writing a whole manpage and then reminding you to actually read ./sound/soc/fsl/fsl_spdif.c β€” but like, do it. the struct is only half the story πŸ’€

and that's the page, bestie πŸŽ€ sign-off time: this one comes from ./sound/soc/fsl, dated October 2026, and it's the struct fsl_spdif_priv(9) entry in the Kernel API Manual. periodt. πŸ’œπŸŒΈ

πŸ“¦ where this page comes from