STRUCT FSL_ESAI(9)
π struct fsl_esai(9) β like, the whole vibe
okay so bestie, this is a page straight out of the Kernel API Manual β it's the manpage for struct fsl_esai(9), and no cap, it's just the private data blob for the ESAI driver. think of it as the driver's little purse where it keeps literally everything it needs πβ¨
πΈ NAME πΈ
struct fsl_esai β ESAI private data. that's it, that's the whole name. it's the driver's personal stash of state, and we're about to open it up π
β¨ SYNOPSIS β¨
here's the whole struct, character for character, don't touch it, she's perfect:
struct fsl_esai {
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct platform_device *pdev;
struct regmap *regmap;
struct clk *coreclk;
struct clk *extalclk;
struct clk *fsysclk;
struct clk *spbaclk;
struct work_struct work;
const struct fsl_esai_soc_data *soc;
spinlock_t lock;
u32 fifo_depth;
u32 slot_width;
u32 slots;
u32 tx_mask;
u32 rx_mask;
u32 channels[2];
u32 hck_rate[2];
u32 sck_rate[2];
bool hck_dir[2];
bool sck_div[2];
bool consumer_mode;
bool synchronous;
char name[32];
};
π¦ MEMBERS π¦
okay, member-by-member tour, let's go β each one gets its moment π
dma_params_rxβ DMA parameters for the receive channel π₯dma_params_txβ DMA parameters for the transmit channel π€pdevβ platform device pointer, the classicregmapβ the regmap handler, aka how we poke registerscoreclkβ clock source to access the register πextalclkβ esai clock source, used to derive HCK, SCK and FSfsysclkβ system clock source, also used to derive HCK, SCK and FSspbaclkβ SPBA clock (optional, depending on SoC design β so, like, sometimes she shows up) πworkβ work to handle the reset operation πsocβ soc specific data, the per-SoC lorelockβ spin lock betweenhw_resetand trigger πfifo_depthβ depth of tx/rx FIFOslot_widthβ width of each DAI slot πslotsβ number of slotstx_maskβ slot mask for TXrx_maskβ slot mask for RXchannelsβ channel num for tx or rxhck_rateβ clock rate of desired HCKx clock β±οΈsck_rateβ clock rate of desired SCKx clock β±οΈhck_dirβ the direction of HCKx pads β‘οΈsck_divβ if using PSR/PM dividers for SCKx clockconsumer_modeβ if fully using DAI clock consumer mode πsynchronousβ if using tx/rx synchronous modenameβ driver name, the last of the bunch π·οΈ
heads up bestie: quite a few of these are arrays with a[2]βchannels,hck_rate,sck_rate,hck_dir,sck_divβ so it's giving "one for tx, one for rx" energy. that's exactly how the original wrote them, so keep the brackets exactly as-is π
π SEE ALSO π
go read these next, they're the supporting cast and they ate:
- Kernel file
./sound/soc/fsl/fsl_esai.c struct fsl_esai_soc_data(9)fsl_esai_divisor_cal(9)fsl_esai_set_dai_sysclk(9)fsl_esai_set_bclk(9)
and that's the whole page, bestie, you understood it, periodt π β¨
this little love letter lives in ./sound/soc/fsl, dated October 2026, and it's filed under struct fsl_esai(9) in the Kernel API Manual β mwah, go forth and derive those clocks ππ«Άπ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms