STRUCT FSL_ESAI(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’œ struct fsl_esai(9) β€” like, the whole vibe

okay so bestie, this is a page straight out of the Kernel API Manual β€” it's the manpage for struct fsl_esai(9), and no cap, it's just the private data blob for the ESAI driver. think of it as the driver's little purse where it keeps literally everything it needs πŸ‘œβœ¨


🌸 NAME 🌸

struct fsl_esai β€” ESAI private data. that's it, that's the whole name. it's the driver's personal stash of state, and we're about to open it up πŸŽ€


✨ SYNOPSIS ✨

here's the whole struct, character for character, don't touch it, she's perfect:

struct fsl_esai {
    struct snd_dmaengine_dai_dma_data dma_params_rx;
    struct snd_dmaengine_dai_dma_data dma_params_tx;
    struct platform_device *pdev;
    struct regmap *regmap;
    struct clk *coreclk;
    struct clk *extalclk;
    struct clk *fsysclk;
    struct clk *spbaclk;
    struct work_struct work;
    const struct fsl_esai_soc_data *soc;
    spinlock_t lock;
    u32 fifo_depth;
    u32 slot_width;
    u32 slots;
    u32 tx_mask;
    u32 rx_mask;
    u32 channels[2];
    u32 hck_rate[2];
    u32 sck_rate[2];
    bool hck_dir[2];
    bool sck_div[2];
    bool consumer_mode;
    bool synchronous;
    char name[32];
 };

πŸ¦‹ MEMBERS πŸ¦‹

okay, member-by-member tour, let's go β€” each one gets its moment πŸ’…

  • dma_params_rx β€” DMA parameters for the receive channel πŸ“₯
  • dma_params_tx β€” DMA parameters for the transmit channel πŸ“€
  • pdev β€” platform device pointer, the classic
  • regmap β€” the regmap handler, aka how we poke registers
  • coreclk β€” clock source to access the register πŸ”‘
  • extalclk β€” esai clock source, used to derive HCK, SCK and FS
  • fsysclk β€” system clock source, also used to derive HCK, SCK and FS
  • spbaclk β€” SPBA clock (optional, depending on SoC design β€” so, like, sometimes she shows up) πŸ™ˆ
  • work β€” work to handle the reset operation πŸ”
  • soc β€” soc specific data, the per-SoC lore
  • lock β€” spin lock between hw_reset and trigger πŸ”’
  • fifo_depth β€” depth of tx/rx FIFO
  • slot_width β€” width of each DAI slot πŸ“
  • slots β€” number of slots
  • tx_mask β€” slot mask for TX
  • rx_mask β€” slot mask for RX
  • channels β€” channel num for tx or rx
  • hck_rate β€” clock rate of desired HCKx clock ⏱️
  • sck_rate β€” clock rate of desired SCKx clock ⏱️
  • hck_dir β€” the direction of HCKx pads ➑️
  • sck_div β€” if using PSR/PM dividers for SCKx clock
  • consumer_mode β€” if fully using DAI clock consumer mode πŸ‘‘
  • synchronous β€” if using tx/rx synchronous mode
  • name β€” driver name, the last of the bunch 🏷️
heads up bestie: quite a few of these are arrays with a [2] β€” channels, hck_rate, sck_rate, hck_dir, sck_div β€” so it's giving "one for tx, one for rx" energy. that's exactly how the original wrote them, so keep the brackets exactly as-is πŸ’–

🌈 SEE ALSO 🌈

go read these next, they're the supporting cast and they ate:


and that's the whole page, bestie, you understood it, periodt πŸ’…βœ¨

this little love letter lives in ./sound/soc/fsl, dated October 2026, and it's filed under struct fsl_esai(9) in the Kernel API Manual β€” mwah, go forth and derive those clocks πŸŽ€πŸ«ΆπŸ’œ

πŸ“¦ where this page comes from