STRUCT EXYNOS_CPUCLK_CFG_DATA(9)

🎀 struct exynos_cpuclk_cfg_data(9) 🎀

okay bestie, welcome to the Kernel API Manual — this one's a struct page from the kernel structs crew, and honestly it's a little cutie. it's giving "small but does her job perfectly." let's get into it 💅

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✨ NAME ✨

struct exynos_cpuclk_cfg_data — config data to setup cpu clocks 🌸

like, literally the little data bundle that tells the cpu clocks how to configure themselves. no cap.

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🦋 SYNOPSIS 🦋

struct exynos_cpuclk_cfg_data {
    unsigned long   prate;
    unsigned long   div0;
    unsigned long   div1;
 };

three unsigned long fields, that's the whole vibe. iconic minimalism fr fr.

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💖 Members 💖

• prate — the frequency of the primary parent clock, in KHz ⭐ (yes babes, KHz, keep that in mind)
• div0 — the value that gets programmed into the div_cpu0 register 🎀
• div1 — the value that gets programmed into the div_cpu1 register 💫

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🌈 Description 🌈

okay so here's the tea ☕ — this structure holds the divider configuration data for the dividers in the CPU clock domain. the parent frequency at which these divider values are valid is specified in prate, and prate is the frequency of the primary parent clock. iykyk.

and here's the important lil caveat bestie: for CPU clock domains that do not have a DIV1 register, the div1 member value is not used 🙈. so don't come for her, she's just sitting there unused. no drama.

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👑 SEE ALSO 👑

• Kernel file ./drivers/clk/samsung/clk-cpu.h
• enum exynos_cpuclk_layout(9)

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and that's the whole page, bestie, you ate that 🫶 stay hydrated, read your headers, and remember: dividers are temporary, but the kernel is forever 💜

this lil love letter came from ./drivers/clk/samsung, dated October 2026 — signed, sealed, delivered as struct exyn...clk_cfg_data(9) ✨🎀✨