STRUCT EXYNOS5_USBDRD_PHY(9)

💅 struct exynos5_usbdrd_phy

okay so bestie, this is a Kernel API Manual page for struct exynos5_usbdrd_phy(9) — it's literally the driver data home for the USB 3.0 PHY, and we're about to read it together like it's the group chat lore 🫶

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✨ NAME ✨

struct exynos5_usbdrd_phy — driver data for USB 3.0 PHY. that's it, that's the whole vibe: it's the struct that holds everything the driver needs to know about the PHY 💖

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🌸 SYNOPSIS 🌸

here's the whole struct, no cap, every field exactly where it lives:

struct exynos5_usbdrd_phy {
    struct device *dev;
    void __iomem *reg_phy;
    void __iomem *reg_pcs;
    void __iomem *reg_pma;
    struct clk_bulk_data *clks;
    struct clk_bulk_data *core_clks;
    const struct exynos5_usbdrd_phy_drvdata *drv_data;
    struct phy *hs_phy;
    struct mutex phy_mutex;
    struct phy_usb_instance {
      struct phy *phy;
      u32 index;
      struct regmap *reg_pmu;
      u32 pmu_offset;
      const struct exynos5_usbdrd_phy_config *phy_cfg;
    } phys[EXYNOS5_DRDPHYS_NUM];
    u32 extrefclk;
    struct regulator_bulk_data *regulators;
    struct typec_switch_dev *sw;
    enum typec_orientation orientation;
 };

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🦋 MEMBERS 🦋

okay now the fun part, member by member, main character energy only 👑

• dev — pointer to the device instance of this platform device. like, this is the "who am I" of the whole thing 🪪
• reg_phy — the usb phy controller register memory base. the address where the register party starts ✨
• reg_pcs — the usb phy physical coding sublayer register memory base. yes, PCS, physical coding sublayer, she has a full name 💅
• reg_pma — the usb phy physical media attachment register memory base. PMA, physical media attachment, also fancy 🎀
• clks — clocks for register access. you need these to even touch the registers, periodt ⏰
• core_clks — core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required). literally the whole list, "as required" and all 🌈
• drv_data — pointer to the SoC level driver data structure. SoC-specific deets live here 🧚
• hs_phy — pointer to the non-Samsung IP high-speed phy controller. not Samsung's IP, so it gets its own pointer 🫶
• phy_mutex — mutex protecting phy_init/exit & TCPC callbacks. she's the bouncer keeping things from colliding 🔒
• phys — array for 'EXYNOS5_DRDPHYS_NUM' number of PHY instances, each with its 'phy' and 'phy_cfg'. and inside each one there's struct phy *phy, u32 index, struct regmap *reg_pmu, u32 pmu_offset, and const struct exynos5_usbdrd_phy_config *phy_cfg — a whole little nested struct, we love a struct within a struct 😭
• extrefclk — frequency select settings when using 'separate reference clocks' for SS and HS operations. SS and HS, both of them, separate clocks, iconic 💫
• regulators — regulators for phy. give the phy her power, she deserves it ⚡
• sw — TypeC orientation switch handle. flips things around, lowkey 🔄
• orientation — TypeC connector orientation — normal or flipped. just those two, normal or flipped, no in-between 🙈

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🔥 SEE ALSO 🔥

want the source? go look at the kernel file ./drivers/phy/samsung/phy-exynos5-usbdrd.c — that's where this whole thing actually lives, iykyk 📁

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ngl bestie, this is a kernel struct doc so the "danger" is mostly "read the fields before you poke them", but fr fr: the phy_mutex is there for a reason, respect the mutex 💀

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and that's the tea 🍓 this page came from ./drivers/phy/samsung, dated October 2026, and it's literally titled struct exynos5_usbdrd_phy(9) — ate and left no crumbs 👑💖✨