STRUCT EP93XX_SPI(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– struct ep93xx_spi(9) πŸ’–

okay so first things first, bestie: this is a page from the Kernel API Manual, and it's literally all about struct ep93xx_spi, aka the EP93xx SPI controller structure. yes, the actual struct. the whole vibe is "here's the struct, here's every field, don't touch anything you don't understand." iconic behavior honestly πŸŽ€


✨ NAME ✨

struct ep93xx_spi β€” the EP93xx SPI controller structure, no cap πŸ¦‹


🌸 SYNOPSIS 🌸

here's the whole thing, character for character, do NOT come for me about the alignment:

struct ep93xx_spi {
    struct clk                      *clk;
    void __iomem                    *mmio;
    unsigned long                   sspdr_phys;
    size_t tx;
    size_t rx;
    size_t fifo_level;
    struct dma_chan                 *dma_rx;
    struct dma_chan                 *dma_tx;
    struct sg_table                 rx_sgt;
    struct sg_table                 tx_sgt;
    void *zeropage;
 };

she's got range, she's got pointers, she's got a void * at the end like a little mystery πŸ•΅οΈβ€β™€οΈ


πŸ’… Members πŸ’…

okay now the part you actually came for β€” the member-by-member breakdown. every single one. let's go πŸ”₯

  • clk β€” the clock for the controller. the heartbeat. the main character energy of the whole struct ⏰
  • mmio β€” pointer to the ioremap'd registers. that's where the actual hardware lives, bestie, so handle with care 🫢
  • sspdr_phys β€” the physical address of the SSPDR register. like a home address but for a register 🏠
  • tx β€” the current byte in the transfer that needs to transmit. she's sending πŸ“€
  • rx β€” the current byte in the transfer that needs to receive. she's receiving πŸ“₯
  • fifo_level β€” how full is FIFO, and the range is literally 0..SPI_FIFO_SIZE - 1. important detail: receiving one frame decreases this level and sending one frame increases it. yes that's the actual direction, don't @ me πŸ’€
  • dma_rx β€” the RX DMA channel. she receives, but make it hardware 🌈
  • dma_tx β€” the TX DMA channel. she transmits, but make it hardware ✨
  • rx_sgt β€” the sg table for RX transfers. the receipts, organized 🧾
  • tx_sgt β€” the sg table for TX transfers. the other receipts, also organized 🧾
  • zeropage β€” a dummy page used as the RX buffer when only the TX buffer is passed in by the client. a little stand-in, a little understudy, a little "we move" 🎭
fr fr though: fifo_level is the one to keep your eyes on. receive one frame, level goes down. send one frame, level goes up. that's the whole mechanic, memorise it πŸ‘‘

πŸ¦‹ SEE ALSO πŸ¦‹

go read these next, iykyk:


that's the whole page, bestie, you ate it up πŸ’– this little masterpiece lives in ./drivers/spi, dated October 2026, and it's filed under struct ep93xx_spi(9) β€” anyway mwah, go read your kernel source, periodt πŸ’…πŸŒΈ

πŸ“¦ where this page comes from