STRUCT EP93XX_DMA_CHAN(9)
π struct ep93xx_dma_chan(9) π
okay so bestie, welcome to the Kernel API Manual β¨ today we're learning about struct ep93xx_dma_chan β literally an EP93xx DMA M2P/M2M channel, and she is that girl π
β¨ NAME β¨
struct ep93xx_dma_chan β an EP93xx DMA M2P/M2M channel π
π¦ SYNOPSIS π¦
struct ep93xx_dma_chan {
struct dma_chan chan;
const struct ep93xx_dma_engine *edma;
void __iomem *regs;
struct ep93xx_dma_chan_cfg dma_cfg;
int irq;
struct clk *clk;
struct tasklet_struct tasklet;
spinlock_t lock;
unsigned long flags;
#define EP93XX_DMA_IS_CYCLIC 0;
int buffer;
struct list_head active;
struct list_head queue;
struct list_head free_list;
u32 runtime_addr;
u32 runtime_ctrl;
struct dma_slave_config slave_config;
};
she's got range, she's got fields, she's iconic π
πΈ Members πΈ
chanβ the dmaengine API channel, the main character of the whole struct fr fr πedmaβ pointer to the engine device, iykyk π§regsβ memory mapped registers, lowkey where the magic happens β¨dma_cfgβ channel number, direction β the whole vibe check of this channel πirqβ interrupt number of the channel π¦clkβ clock used by this channel, she needs her energy βtaskletβ channel specific tasklet used for callbacks πlockβ lock protecting the fields following π (respect her boundaries bestie)flagsβ flags for the channel πbufferβ which buffer to use next (0/1), a little binary moment πactiveβ flattened chain of descriptors currently being processed π₯queueβ pending descriptors which are handled next, the waiting room π«Άfree_listβ list of free descriptors which can be used, the available pool πruntime_addrβ physical address currently used as dest/src (M2M only). This is set via.device_configbefore slave operation is prepared πruntime_ctrlβ M2M runtime values for the control register πslave_configβ slave configuration π
β Description β
so here's the tea β the EP93xx DMA controller doesn't support real chained DMA descriptors, so we will have a slightly different scheme here: active points to a head of flattened DMA descriptor chain π«
queue holds pending transactions. These are linked through the first descriptor in the chain. When a descriptor is moved to the active queue, the first and chained descriptors are flattened into a single list π₯ β no cap, that's literally how she works β¨
π SEE ALSO π
- Kernel file
./drivers/dma/ep93xx_dma.cstruct ep93xx_dma_desc(9),struct ep93xx_dma_engine(9),ep93xx_dma_set_active(9),ep93xx_dma_advance_active(9),ep93xx_dma_advance_work(9),ep93xx_dma_tx_submit(9),ep93xx_dma_alloc_chan_resources(9),ep93xx_dma_free_chan_resources(9),ep93xx_dma_prep_dma_memcpy(9),ep93xx_dma_prep_slave_sg(9),ep93xx_dma_prep_dma_cyclic(9),ep93xx_dma_synchronize(9),ep93xx_dma_terminate_all(9),ep93xx_dma_tx_status(9),ep93xx_dma_issue_pending(9)π
go read those fr fr, they're all linked in the same ./drivers/dma cinematic universe π¬
okay bestie that's the whole page, hope u slayed the vibe check π this came straight out of ./drivers/dma, dated October 2026, and it's part of the Kernel API Manual β mwah, study up, ily, bye πβ¨π
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms