STRUCT EP93XX_DMA_CHAN(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– struct ep93xx_dma_chan(9) πŸ’–

okay so bestie, welcome to the Kernel API Manual ✨ today we're learning about struct ep93xx_dma_chan β€” literally an EP93xx DMA M2P/M2M channel, and she is that girl πŸŽ€


✨ NAME ✨

struct ep93xx_dma_chan β€” an EP93xx DMA M2P/M2M channel πŸ‘‘


πŸ¦‹ SYNOPSIS πŸ¦‹

struct ep93xx_dma_chan {
    struct dma_chan                 chan;
    const struct ep93xx_dma_engine  *edma;
    void __iomem                    *regs;
    struct ep93xx_dma_chan_cfg      dma_cfg;
    int irq;
    struct clk                      *clk;
    struct tasklet_struct           tasklet;
    spinlock_t lock;
    unsigned long                   flags;
  #define EP93XX_DMA_IS_CYCLIC            0;
    int buffer;
    struct list_head                active;
    struct list_head                queue;
    struct list_head                free_list;
    u32 runtime_addr;
    u32 runtime_ctrl;
    struct dma_slave_config         slave_config;
 };

she's got range, she's got fields, she's iconic πŸ’…


🌸 Members 🌸

  • chan β€” the dmaengine API channel, the main character of the whole struct fr fr πŸ‘‘
  • edma β€” pointer to the engine device, iykyk 🧚
  • regs β€” memory mapped registers, lowkey where the magic happens ✨
  • dma_cfg β€” channel number, direction β€” the whole vibe check of this channel πŸŽ€
  • irq β€” interrupt number of the channel πŸ¦‹
  • clk β€” clock used by this channel, she needs her energy ⭐
  • tasklet β€” channel specific tasklet used for callbacks πŸ’–
  • lock β€” lock protecting the fields following πŸ”’ (respect her boundaries bestie)
  • flags β€” flags for the channel 🌈
  • buffer β€” which buffer to use next (0/1), a little binary moment πŸ’€
  • active β€” flattened chain of descriptors currently being processed πŸ”₯
  • queue β€” pending descriptors which are handled next, the waiting room 🫢
  • free_list β€” list of free descriptors which can be used, the available pool πŸ“
  • runtime_addr β€” physical address currently used as dest/src (M2M only). This is set via .device_config before slave operation is prepared πŸ™ˆ
  • runtime_ctrl β€” M2M runtime values for the control register πŸ’œ
  • slave_config β€” slave configuration πŸ’…

⭐ Description ⭐

so here's the tea β˜• the EP93xx DMA controller doesn't support real chained DMA descriptors, so we will have a slightly different scheme here: active points to a head of flattened DMA descriptor chain πŸ’«

queue holds pending transactions. These are linked through the first descriptor in the chain. When a descriptor is moved to the active queue, the first and chained descriptors are flattened into a single list πŸ”₯ β€” no cap, that's literally how she works ✨


πŸ’œ SEE ALSO πŸ’œ


go read those fr fr, they're all linked in the same ./drivers/dma cinematic universe 🎬

okay bestie that's the whole page, hope u slayed the vibe check πŸ’– this came straight out of ./drivers/dma, dated October 2026, and it's part of the Kernel API Manual β€” mwah, study up, ily, bye πŸ‘‘βœ¨πŸŽ€

πŸ“¦ where this page comes from