STRUCT DWC2_HOST_CHAN(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸŽ€ NAME πŸŽ€

struct dwc2_host_chan β€” Software host channel descriptor πŸ’…

okay bestie, welcome to the struct dwc2_host_chan(9) page from the Kernel API Manual. This is literally the software host channel descriptor β€” the struct that keeps a single host channel’s whole vibe together. 🫢


✨ SYNOPSIS ✨

struct dwc2_host_chan {
    u8 hc_num;
    unsigned dev_addr:7;
    unsigned ep_num:4;
    unsigned ep_is_in:1;
    unsigned speed:4;
    unsigned ep_type:2;
    unsigned max_packet:11;
    unsigned data_pid_start:2;
  #define DWC2_HC_PID_DATA0       TSIZ_SC_MC_PID_DATA0;
  #define DWC2_HC_PID_DATA2       TSIZ_SC_MC_PID_DATA2;
  #define DWC2_HC_PID_DATA1       TSIZ_SC_MC_PID_DATA1;
  #define DWC2_HC_PID_MDATA       TSIZ_SC_MC_PID_MDATA;
  #define DWC2_HC_PID_SETUP       TSIZ_SC_MC_PID_SETUP;
    unsigned multi_count:2;
    u8 *xfer_buf;
    dma_addr_t xfer_dma;
    dma_addr_t align_buf;
    u32 xfer_len;
    u32 xfer_count;
    u16 start_pkt_count;
    u8 xfer_started;
    u8 do_ping;
    u8 error_state;
    u8 halt_on_queue;
    u8 halt_pending;
    u8 do_split;
    u8 complete_split;
    u8 hub_addr;
    u8 hub_port;
    u8 xact_pos;
  #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID;
  #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END;
  #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN;
  #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL;
    u8 requests;
    u8 schinfo;
    u16 ntd;
    enum dwc2_halt_status halt_status;
    u32 hcint;
    struct dwc2_qh *qh;
    struct list_head hc_list_entry;
    dma_addr_t desc_list_addr;
    u32 desc_list_sz;
    struct list_head split_order_list_entry;
};

πŸ’– Members πŸ’–

Here’s the member-by-member breakdown, no skipping, periodt:

  • hc_num β€” Host channel number, used for register address lookup. πŸ”Ž
  • dev_addr β€” Address of the device.
  • ep_num β€” Endpoint of the device.
  • ep_is_in β€” Endpoint direction.
  • speed β€” Device speed. One of the following values:
    • USB_SPEED_LOW
    • USB_SPEED_FULL
    • USB_SPEED_HIGH
  • ep_type β€” Endpoint type. One of the following values:
    • USB_ENDPOINT_XFER_CONTROL: 0
    • USB_ENDPOINT_XFER_ISOC: 1
    • USB_ENDPOINT_XFER_BULK: 2
    • USB_ENDPOINT_XFER_INTR: 3
  • max_packet β€” Max packet size in bytes.
  • data_pid_start β€” PID for initial transaction. 0: DATA0, 1: DATA2, 2: DATA1, 3: MDATA (non-Control EP), SETUP (Control EP).
  • multi_count β€” Number of additional periodic transactions per (micro)frame.
  • xfer_buf β€” Pointer to current transfer buffer position.
  • xfer_dma β€” DMA address of xfer_buf.
  • align_buf β€” In Buffer DMA mode this will be used if xfer_buf is not DWORD aligned.
  • xfer_len β€” Total number of bytes to transfer.
  • xfer_count β€” Number of bytes transferred so far.
  • start_pkt_count β€” Packet count at start of transfer.
  • xfer_started β€” True if the transfer has been started.
  • do_ping β€” True if a PING request should be issued on this channel.
  • error_state β€” True if the error count for this transaction is non-zero.
  • halt_on_queue β€” True if this channel should be halted the next time a request is queued for the channel. This is necessary in slave mode if no request queue space is available when an attempt is made to halt the channel.
  • halt_pending β€” True if the host channel has been halted, but the core is not finished flushing queued requests.
  • do_split β€” Enable split for the channel.
  • complete_split β€” Enable complete split.
  • hub_addr β€” Address of high speed hub for the split.
  • hub_port β€” Port of the low/full speed device for the split.
  • xact_pos β€” Split transaction position. One of the following values:
    • DWC2_HCSPLT_XACTPOS_MID
    • DWC2_HCSPLT_XACTPOS_BEGIN
    • DWC2_HCSPLT_XACTPOS_END
    • DWC2_HCSPLT_XACTPOS_ALL
  • requests β€” Number of requests issued for this channel since it was assigned to the current transfer (not counting PINGs).
  • schinfo β€” Scheduling micro-frame bitmap.
  • ntd β€” Number of transfer descriptors for the transfer.
  • halt_status β€” Reason for halting the host channel.
  • hcint β€” Contents of the HCINT register when the interrupt came.
  • qh β€” QH for the transfer being processed by this channel.
  • hc_list_entry β€” For linking to list of host channels.
  • desc_list_addr β€” Current QH’s descriptor list DMA address.
  • desc_list_sz β€” Current QH’s descriptor list size.
  • split_order_list_entry β€” List entry for keeping track of the order of splits.

🌈 Description 🌈

This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel. Iconic little state blob, honestly. ✨


πŸ¦‹ SEE ALSO πŸ¦‹


k bye bestie β€” this page comes from ./drivers/usb/dwc2, dated October 2026, and it’s the struct dwc2_host_chan(9) manual. slay and read the source πŸ’–βœ¨

πŸ“¦ where this page comes from