STRUCT DWC2_CORE_PARAMS(9)

🌸 NAME 🌸

hii bestie 💖 this is the manual page for struct dwc2_core_params(9) from the Kernel API Manual, and it is literally the config blueprint for the core — no cap. The official name vibe is struct dwc2_core_params — Parameters for configuring the core. It’s giving “one struct to hold all the knobs” energy, and we are obsessed 🎀

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✨ SYNOPSIS ✨

okay so the synopsis is this entire struct, and yes every field and every #define matters, so here it is exactly — character for character, bestie 🫶

       struct dwc2_core_params {
           struct usb_otg_caps otg_caps;
           u8 phy_type;
         #define DWC2_PHY_TYPE_PARAM_FS          0;
         #define DWC2_PHY_TYPE_PARAM_UTMI        1;
         #define DWC2_PHY_TYPE_PARAM_ULPI        2;
           u8 speed;
         #define DWC2_SPEED_PARAM_HIGH   0;
         #define DWC2_SPEED_PARAM_FULL   1;
         #define DWC2_SPEED_PARAM_LOW    2;
           u8 phy_utmi_width;
           bool eusb2_disc;
           bool phy_ulpi_ddr;
           bool phy_ulpi_ext_vbus;
           bool enable_dynamic_fifo;
           bool en_multiple_tx_fifo;
           bool i2c_enable;
           bool acg_enable;
           bool ulpi_fs_ls;
           bool ts_dline;
           bool reload_ctl;
           bool uframe_sched;
           bool external_id_pin_ctl;
           int power_down;
         #define DWC2_POWER_DOWN_PARAM_NONE              0;
         #define DWC2_POWER_DOWN_PARAM_PARTIAL           1;
         #define DWC2_POWER_DOWN_PARAM_HIBERNATION       2;
           bool no_clock_gating;
           bool lpm;
           bool lpm_clock_gating;
           bool besl;
           bool hird_threshold_en;
           bool service_interval;
           u8 hird_threshold;
           bool activate_stm_fs_transceiver;
           bool activate_stm_id_vb_detection;
           bool activate_ingenic_overcurrent_detection;
           bool ipg_isoc_en;
           u16 max_packet_count;
           u32 max_transfer_size;
           u32 ahbcfg;
           u32 ref_clk_per;
           u16 sof_cnt_wkup_alert;
           bool host_dma;
           bool dma_desc_enable;
           bool dma_desc_fs_enable;
           bool host_support_fs_ls_low_power;
           bool host_ls_low_power_phy_clk;
           bool oc_disable;
           u8 host_channels;
           u16 host_rx_fifo_size;
           u16 host_nperio_tx_fifo_size;
           u16 host_perio_tx_fifo_size;
           bool g_dma;
           bool g_dma_desc;
           u32 g_rx_fifo_size;
           u32 g_np_tx_fifo_size;
           u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
           bool change_speed_quirk;
        };

🧚 MEMBERS 🧚

okay bestie, this is the part everyone actually scrolls to — literally every single knob on this struct, one by one, no skipping. there are a LOT. hydrate first. 🍓

• otg_caps — tells the world what OTG stuff your hardware actually has. these are the OTG caps pulled from the platform parameters, and they're used to set up:
  • HNP and SRP capable
  • SRP Only capable
  • No HNP/SRP capable (always available) — defaults to the best available option
  • the OTG revision number the device is compliant with, in binary-coded decimal (so like, 2.0 is 0200H) — see struct usb_otg_caps
• phy_type — which PHY interface to use. left unspecified, the driver will auto-detect the phy_type for you, main character energy.
  • 0 — Full Speed Phy
  • 1 — UTMI+ Phy
  • 2 — ULPI Phy

defaults to the best available option (2, then 1, then 0).

• speed — the maximum speed of operation in host and device mode. the actual speed depends on the speed of the attached device and on the value of phy_type, so it's giving "it depends" but make it official.
  • 0 — High Speed (default when phy_type is UTMI+ or ULPI)
  • 1 — Full Speed (default when phy_type is Full Speed)
• phy_utmi_width — the UTMI+ Data Width (in bits). this one is applicable for a phy_type of UTMI+ or ULPI. (for a ULPI phy_type, it indicates the data width between the MAC and the ULPI Wrapper.) also it's applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits" — meaning the core has been configured to work at either data path width.
  • 8 or 16 (default 16 if available)
• eusb2_disc — whether the eUSB2 PHY disconnect support flow is applicable or not. only applicable in device mode of HSOTG and HS IOT cores v5.00 or higher, so check your core's birth year first. 👑
  • 0 — eUSB2 PHY disconnect support flow not applicable
  • 1 — eUSB2 PHY disconnect support flow applicable
• phy_ulpi_ddr — whether the ULPI operates at double or single data rate. only applicable if phy_type is ULPI, no exceptions.
  • 0 — single data rate ULPI interface with 8 bit wide data bus (default)
  • 1 — double data rate ULPI interface with 4 bit wide data bus
• phy_ulpi_ext_vbus — for a ULPI phy, whether to use the internal or external supply to drive the VBus.
  • 0 — Internal supply (default)
  • 1 — External supply
• enable_dynamic_fifo — do we let the FIFOs get flexible or not.
  • 0 — Use coreConsultant-specified FIFO size parameters
  • 1 — Allow dynamic FIFO sizing (default, if available)
• en_multiple_tx_fifo — specifies whether dedicated per-endpoint transmit FIFOs are enabled for non-periodic IN endpoints in device mode. that's it, that's the whole vibe.
• i2c_enable — whether to use the I2C interface for a full speed PHY. only applicable if phy_type is FS.
  • 0 — No (default)
  • 1 — Yes
• acg_enable — for enabling Active Clock Gating in the controller.
  • 0 — No
  • 1 — Yes
• ulpi_fs_ls — make the ULPI phy operate in FS/LS mode only.
  • 0 — No (default)
  • 1 — Yes
• ts_dline — enable Term Select Dline pulsing.
  • 0 — No (default)
  • 1 — Yes
• reload_ctl — allow dynamic reloading of the HFIR register during runtime. yes, at runtime. iconic.
  • 0 — No (default for core < 2.92a)
  • 1 — Yes (default for core >= 2.92a)
• uframe_sched — true to enable the microframe scheduler. short and sweet, love that for us.
• external_id_pin_ctl — specifies whether the ID pin is handled externally. disable the CONIDSTSCHNG controller interrupt in such case, fr fr.
  • 0 — No (default)
  • 1 — Yes
• power_down — whether the controller supports power_down. if it's enabled, the controller will enter power_down in both peripheral and host mode when needed.
  • 0 — No (default)
  • 1 — Partial power down
  • 2 — Hibernation
• no_clock_gating — whether to avoid the clock gating feature.
  • 0 — No (use clock gating)
  • 1 — Yes (avoid it)
• lpm — enable LPM support.
  • 0 — No
  • 1 — Yes
• lpm_clock_gating — enable core PHY clock gating.
  • 0 — No
  • 1 — Yes
• besl — enable LPM Errata support.
  • 0 — No
  • 1 — Yes
• hird_threshold_en — HIRD or HIRD Threshold enable.
  • 0 — No
  • 1 — Yes
• service_interval — enable service interval based scheduling.
  • 0 — No
  • 1 — Yes
• hird_threshold — value of BESL or HIRD Threshold. literally just the value. 💅
• activate_stm_fs_transceiver — activate the internal transceiver using the GGPIO register.
  • 0 — Deactivate the transceiver (default)
  • 1 — Activate the transceiver
• activate_stm_id_vb_detection — activate external ID pin and Vbus level detection using the GGPIO register.
  • 0 — Deactivate the external level detection (default)
  • 1 — Activate the external level detection
• activate_ingenic_overcurrent_detection — activate Ingenic overcurrent detection.
  • 0 — Deactivate the overcurrent detection
  • 1 — Activate the overcurrent detection (default)
• ipg_isoc_en — indicates whether the IPG supports is enabled or disabled.
  • 0 — Disable (default)
  • 1 — Enable
• max_packet_count — the maximum number of packets in a transfer, 15 to 511. the actual maximum value is autodetected and is also the default, so it kinda handles itself.
• max_transfer_size — the maximum transfer size supported, in bytes, 2047 to 65,535. actual maximum value is autodetected and also the default. same deal.
• ahbcfg — this field lets you override the default value of the GAHBCFG register.
  • -1 — GAHBCFG value will be set to 0x06 (INCR, default)
  • all others — GAHBCFG value will be overridden with this value

not all bits can be controlled like this, bestie — the bits defined by GAHBCFG_CTRL_MASK are controlled by the driver and are ignored in this configuration value. don't fight the driver, you will lose.

• ref_clk_per — the period of ref_clk, in pico seconds.
  • 62500 — 16MHz
  • 58823 — 17MHz
  • 52083 — 19.2MHz
  • 50000 — 20MHz
  • 41666 — 24MHz
  • 33333 — 30MHz (default)
  • 25000 — 40MHz
• sof_cnt_wkup_alert — the number of SOF's after which the controller should generate an interrupt if the device had been in L1 state until that period. this is used by SW to initiate Remote WakeUp in the controller so as to sync to the uF number from the host. big "wake up bestie, the host is calling" energy. ⭐
• host_dma — whether to use slave or DMA mode for accessing the data FIFOs. the driver will automatically detect the value for this parameter if none is specified.
  • 0 — Slave (always available)
  • 1 — DMA (default, if available)
• dma_desc_enable — when DMA mode is enabled, whether to use address DMA mode or descriptor DMA mode for accessing the data FIFOs. the driver auto-detects this too if you say nothing.
  • 0 — Address DMA
  • 1 — Descriptor DMA (default, if available)
• dma_desc_fs_enable — same question as above but for Full Speed mode only: address DMA or descriptor DMA for accessing the data FIFOs. auto-detected if unspecified.
  • 0 — Address DMA
  • 1 — Descriptor DMA in FS (default, if available)
• host_support_fs_ls_low_power — whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
  • 0 — Don't support low power mode (default)
  • 1 — Support low power mode
• host_ls_low_power_phy_clk — the PHY clock rate in low power mode when connected to a Low Speed device in host mode. only applicable if host_support_fs_ls_low_power is enabled.
  • 0 — 48 MHz (default when phy_type is UTMI+ or ULPI)
  • 1 — 6 MHz (default when phy_type is Full Speed)
• oc_disable — flag to disable the overcurrent condition.
  • 0 — Allow overcurrent condition to get detected
  • 1 — Disable overcurrent condtion to get detected
• host_channels — the number of host channel registers to use, 1 to 16. actual maximum value is autodetected and also the default. yes, again.
• host_rx_fifo_size — number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled, 16 to 32768. actual maximum value is autodetected and also the default.
• host_nperio_tx_fifo_size — number of 4-byte words in the non-periodic Tx FIFO in host mode when dynamic FIFO sizing is enabled, 16 to 32768. actual maximum value is autodetected and also the default.
• host_perio_tx_fifo_size — number of 4-byte words in the periodic Tx FIFO in host mode when dynamic FIFO sizing is enabled, 16 to 32768. actual maximum value is autodetected and also the default.
• g_dma — enables gadget dma usage (default: autodetect).
• g_dma_desc — enables gadget descriptor DMA (default: autodetect).
• g_rx_fifo_size — the periodic rx fifo size for the device, in DWORDS from 16-32768 (default: 2048 if possible, otherwise autodetect).
• g_np_tx_fifo_size — the non-periodic tx fifo size for the device in DWORDS from 16-32768 (default: 1024 if possible, otherwise autodetect).
• g_tx_fifo_size — an array of TX fifo sizes in dedicated fifo mode. each value corresponds to one EP starting from EP1 (max 15 values). sizes are in DWORDS with possible values from 16-32768 (default: 256, 256, 256, 256, 768, 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
• change_speed_quirk — change the speed configuration to DWC2_SPEED_PARAM_FULL while a full/low speed device is connected. and change the speed back to DWC2_SPEED_PARAM_HIGH while the device is gone.
  • 0 — No (default)
  • 1 — Yes

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🌈 DESCRIPTION 🌈

so here's the tea: the parameters above can all be specified when starting the module, and they define how the DWC_otg controller should be configured. 🫶

and here's the safety net — a value of -1 (or any other out of range value) for any parameter means "read the value from hardware (if possible), or just use the builtin default described above." so if you're not sure, you can absolutely just vibe with -1 and let the hardware speak for itself. no cap.

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💜 SEE ALSO 💜

• Kernel file ./drivers/usb/dwc2/core.h
• struct dwc2_hsotg_ep(9)
• struct dwc2_hsotg_req(9)
• struct dwc2_hw_params(9)
• struct dwc2_gregs_backup(9)
• struct dwc2_dregs_backup(9)
• struct dwc2_hregs_backup(9)
• struct dwc2_hsotg(9)

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and that's the whole page bestie, you made it to the end 🎀 this little gem lives in ./drivers/usb/dwc2, it's dated October 2026, and you're reading page 9 — struct dwc2_core_params(9). go forth and configure responsibly. 💖✨