STRUCT DMUB_CURSOR_OFFLOAD_PIPE_DATA_DCN401_V1(9)

📦 version 7.3.1, in nixpkgs unstable

🎀 struct dmub_cursor_offload_pipe_data_dcn401_v1(9) 🎀

okay bestie, so this page lives in the Kernel API Manual, section 9, and the header up top is literally just truncating the name to struct dmub_...ta_dcn401_v1(9) — the real, full, un-cut name is struct dmub_cursor_offload_pipe_data_dcn401_v1, and honestly? iconic of the manpage renderer to give up halfway. anyway, this is the DCN401 per-pipe cursor data struct and we're gonna go through it field by field. no skipping. 💅

✨ NAME ✨

struct dmub_cursor_offload_pipe_data_dcn401_v1 — DCN401 per pipe data.

that's it, that's the whole vibe. it's per-pipe data, for DCN401, about cursors, offloaded. 🦋

🌸 SYNOPSIS 🌸

here's the whole struct, copied exactly, don't touch anything:

struct dmub_cursor_offload_pipe_data_dcn401_v1 {
    uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS;
    uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH;
    uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16;
    uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16;
    uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16;
    uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16;
    uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16;
    uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16;
    uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13;
    uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1;
    uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3;
    uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1;
    uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2;
    uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5;
    uint32_t reserved0[4];
    uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1;
    uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3;
    uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1;
    uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1;
    uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24;
    uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24;
    uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16;
    uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16;
    uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB
        : 16;
    uint32_t
        CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16;
    uint32_t reserved1[4];
    uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8;
    uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8;
    uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1;
    uint32_t reserved2[3];
};
🫶 quick heads up bestie: that CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, line really does have a comma sitting there right before the : 16. that's how it's written in the source. not a typo on my end, i promise. copy it verbatim or the vibe check fails. 💀

also worth clocking: CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET is a : 13 bitfield, CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK is : 5, the two CM_CUR0_CURSOR0_COLOR0/COLOR1 fields are : 24 each, and the HUBPREQ0_CURSOR_SETTINGS pair is : 8 each. the rest of the small ones are : 1, : 3, : 2, : 16 as shown. there are three reserved arrays — reserved0[4], reserved1[4], reserved2[3] — and yes, reserved2 is only 3. noted. 📝

💜 DESCRIPTION 💜

lowkey this struct is the whole per-pipe cursor-offload bundle for DCN401, and it's giving organized. it's split into distinct little neighborhoods:

  • the CURSOR0_0_* block — the actual cursor hardware registers as the DMUB firmware sees them: CURSOR0_0_CURSOR_SURFACE_ADDRESS and CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH (the address, split across two 32-bit fields, because of course), then the packed size, position, hot spot, dst offset and control fields, all carved into bitfields with names like CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH and CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE. after that comes reserved0[4] to keep everything lined up. ✨
  • the CM_CUR0_CURSOR0_* block — the color-manager side of the same cursor: control bits (CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE, CUR0_MODE, CUR0_EXPANSION_MODE, CUR0_ROM_EN), two 24-bit color fields CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 and CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1, and the floating-point scale/bias fields CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y, CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB and CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB. then reserved1[4]. 🎀
  • the HUBPREQ0_CURSOR_SETTINGS / HUBP block — HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET, HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST, and the lone MALL flag HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR (a : 1 bit, very "am i in MALL or not" of it). then reserved2[3]. 🌈

the reserved fields aren't described in this page, so i'm not gonna make up stories about them — they're there, they pad the layout, that's all the docs say. ngl, respect for the honesty. 🙈

🦋 OPTIONS 🦋

bestie. it's a struct. there are no options here, there's nothing to pass, don't @ me. the fields in SYNOPSIS are the content. moving on. 💅

🌟 Members 🌟

the page has a Members section and, well, it arrived empty — there's no per-member writeup in this one. so the members are simply the fields listed above in the synopsis, and that's what we've got. delightful, unbothered, moisturized. 💖

🔥 SEE ALSO 🔥

kernel file ./drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h, plus the whole extended friend group — every single one of these, fr fr:

  • union dmub_addr(9)
  • struct dmub_cursor_offload_pipe_data_dcn30_v1(9)
  • struct dmub_cursor_offload_pipe_data_dcn60_v1(9)
  • struct dmub_cursor_offload_pipe_data_v1(9)
  • struct dmub_cursor_offload_payload_data_v1(9)
  • struct dmub_cursor_offload_stream_v1(9)
  • struct dmub_cursor_offload_v1(9)
  • union dmub_fw_meta_feature_bits(9)
  • struct dmub_fw_meta_info(9)
  • union dmub_fw_meta(9)
  • struct dmcub_trace_buf_entry(9)
  • union dmub_fw_boot_status(9)
  • enum dmub_fw_boot_status_bit(9)
  • enum dmub_cursor_offload_comand_type(9)
  • union dmub_fw_boot_options(9)
  • enum dmub_shared_state_feature_id(9)
  • struct dmub_shared_state_ips_fw(9)
  • struct dmub_shared_state_ips_driver(9)
  • struct dmub_shared_state_cursor_offload_v1(9)
  • struct dmub_shared_state_feature_block(9)
  • union dmub_gpint_data_register(9)
  • enum dmub_out_cmd_type(9)
  • struct dmub_cmd_header(9)
  • struct dmub_rb_cmd_common(9)
  • struct dmub_cmd_PLAT_54186_wa(9)
  • struct dmub_rb_cmd_PLAT_54186_wa(9)
  • enum dmub_cmd_mall_type(9)
  • struct dmub_rb_cmd_mall(9)
  • enum dmub_cmd_cab_type(9)
  • struct dmub_rb_cmd_cab_for_ss(9)
  • enum dmub_fams2_allow_delay_check_mode(9)
  • enum dmub_cmd_idle_opt_type(9)
  • struct dmub_rb_cmd_idle_opt_dcn_restore(9)
  • struct dmub_dcn_notify_idle_cntl_data(9)
  • struct dmub_rb_cmd_idle_opt_dcn_notify_idle(9)
  • enum dmub_idle_opt_dc_power_state(9)
  • struct dmub_idle_opt_set_dc_power_state_data(9)
  • struct dmub_rb_cmd_idle_opt_set_dc_power_state(9)
  • struct dmub_clocks(9)
  • enum dmub_cmd_clk_mgr_type(9)
  • struct dmub_rb_cmd_clk_mgr_notify_clocks(9)
  • struct dmub_cmd_digx_encoder_control_data(9)
  • struct dmub_rb_cmd_digx_encoder_control(9)
  • struct dmub_cmd_set_pixel_clock_data(9)
  • struct dmub_cmd_enable_disp_power_gating_data(9)
  • struct dmub_rb_cmd_enable_disp_power_gating(9)
  • struct dmub_dig_transmitter_control_data_v1_7(9)
  • union dmub_cmd_dig1_transmitter_control_data(9)
  • struct dmub_rb_cmd_dig1_transmitter_control(9)
  • struct dmub_rb_cmd_domain_control_data(9)
  • struct dmub_rb_cmd_domain_control(9)
  • struct dmub_rb_cmd_dpphy_init(9)
  • enum dp_aux_request_action(9)
  • enum aux_return_code_type(9)
  • enum aux_channel_type(9)
  • struct aux_transaction_parameters(9)
  • struct dmub_rb_cmd_hpd_sense_notify(9)
  • enum dmub_phy_fsm_state(9)
  • enum dmub_abm_ace_curve_type(9)
  • enum dmub_abm_histogram_type(9)
  • enum dmub_cmd_panel_cntl_type(9)
  • struct dmub_cmd_panel_cntl_data(9)
  • struct dmub_rb_cmd_panel_cntl(9)
  • struct dmub_cmd_cable_id_input(9)
  • struct dmub_cmd_cursor_offload_init_data(9)
  • struct dmub_rb_cmd_cursor_offload_init(9)
  • struct dmub_cmd_cursor_offload_stream_data(9)
  • struct dmub_rb_cmd_cursor_offload_stream_cntl(9)
  • union dmub_rb_cmd(9)
  • union dmub_rb_out_cmd(9)
  • struct dmub_rb_init_params(9)
  • struct dmub_rb(9)
👑 and yes, enum dmub_cursor_offload_comand_type(9) is spelled comand in the source. not my typo, not your typo, we leave it. iykyk.

💫 sign-off 💫

that's the page bestie!! source path came through as ./drivers/gpu/drm/amd/display/... (yep, abbreviated, the house style said so) and the date stamp is October 2026, and the footer also re-echoes struct dmub_...ta_dcn401_v1(9) one last time on the way out. go forth and treat your bitfields with love. mwah. 💖✨🎀🦋🌸💅🫶😭🔥👑🌈⭐💀🙈🍓🧚💜

📦 where this page comes from