STRUCT DIV_HW_DATA(9)

🌸 NAME 🌸

okay bestie, welcome to the struct div_hw_data(9) page in the Kernel API Manual — it's literally struct div_hw_data — divider clock hardware data. no cap, that's the whole vibe.

✨ SYNOPSIS ✨

here's the struct, exactly as it appears so you can vibe-check it:

       struct div_hw_data {
           struct clk_hw_data hw_data;
           const struct clk_div_table *dtable;
           unsigned long invalid_rate;
           unsigned long max_rate;
           u32 width;
        };

🎀 Members 🎀

• hw_data — clock hw data. that's the main character field 💅
• dtable — pointer to divider table. iconic pointer behavior ✨
• invalid_rate — invalid rate for divider. lowkey important 🫶
• max_rate — maximum rate for divider. highkey the ceiling 🌈
• width — divider width. periodt 🎀

💖 SEE ALSO 💖

• Kernel file ./drivers/clk/renesas/rzg2l-cpg.c: struct clk_hw_data(9), struct sd_mux_hw_data(9), struct rzg2l_cpg_priv(9), struct mstop(9), struct mod_clock(9). go read these too bestie, iykyk 🔥

xoxo, your fav kernel bestie 💅 — this page came from ./drivers/clk/renesas, dated October 2026, and it's the struct div_hw_data(9) page. periodt 🫶