STRUCT DENALI_CONTROLLER(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– struct denali_controller(9) πŸ’–

okay so bestie, this is a page from the Kernel API Manual and it's all about struct denali_controller β€” the Denali NAND controller data. genuinely iconic little struct, let's get into it 🫢


✨ NAME ✨

struct denali_controller β€” Denali NAND controller data, no cap πŸ’…


πŸ¦‹ SYNOPSIS πŸ¦‹

struct denali_controller {
    struct nand_controller controller;
    struct device *dev;
    struct list_head chips;
    unsigned long clk_rate;
    unsigned long clk_x_rate;
    void __iomem *reg;
    void __iomem *host;
    struct completion complete;
    int irq;
    u32 irq_mask;
    u32 irq_status;
    spinlock_t irq_lock;
    bool dma_avail;
    int devs_per_cs;
    int oob_skip_bytes;
    int active_bank;
    int nbanks;
    unsigned int revision;
    unsigned int caps;
    const struct nand_ecc_caps *ecc_caps;
    u32 (*host_read)(struct denali_controller *denali, u32 addr);
    void (*host_write)(struct denali_controller *denali, u32 addr, u32
data);
    void (*setup_dma)(struct denali_controller *denali, dma_addr_t
dma_addr, int page, bool write);
 };

like, look at all those fields, she's serving range πŸ’€βœ¨


πŸŽ€ MEMBERS πŸŽ€

bestie, every single one, in order, let's go πŸƒβ€β™€οΈπŸ’¨

  • controller β€” the base NAND controller structure, the main character energy right at the top πŸ‘‘
  • dev β€” the device 🌸
  • chips β€” the list of chips attached to this controller, her little squad fr fr
  • clk_rate β€” frequency of core clock ⏰
  • clk_x_rate β€” frequency of bus interface clock, yes there's a second clock, she's got layers πŸ¦‹
  • reg β€” base of Register Interface
  • host β€” base of Host Data/Command interface
  • complete β€” completion used to wait for interrupts, lowkey just sitting there waiting for a text back 😭
  • irq β€” interrupt number
  • irq_mask β€” interrupt bits the controller is waiting for
  • irq_status β€” interrupt bits of events that have happened, the receipts πŸ“
  • irq_lock β€” lock to protect irq_mask and irq_status, keep those two safe bestie πŸ”’
  • dma_avail β€” set if DMA engine is available βœ…
  • devs_per_cs β€” number of devices connected in parallel
  • oob_skip_bytes β€” number of bytes in OOB skipped by the ECC engine
  • active_bank β€” active bank id 🏦
  • nbanks β€” the number of banks supported by this controller
  • revision β€” IP revision
  • caps β€” controller capabilities that cannot be detected run-time πŸ‘€
  • ecc_caps β€” ECC engine capabilities ✨
  • host_read β€” callback for read access of Host Data/Command Interface
  • host_write β€” callback for write access of Host Data/Command Interface
  • setup_dma β€” callback for setup of the Data DMA πŸ”₯

🌈 SEE ALSO 🌈

go check out the Kernel file ./drivers/mtd/nand/raw/denali.h, plus struct denali_chip_sel(9) and struct denali_chip(9) β€” they're all in the ./drivers/mtd/nand/raw directory and honestly they ate πŸ’…βœ¨


ngl bestie, this whole page lives under ./drivers/mtd/nand/raw β€” that's the neighborhood 🏑

okay that's the whole thing, ily, go read the source πŸ«ΆπŸ’–

β€” sourced from ./drivers/mtd/nand/raw, dated October 2026, with the header calling it struct denali_controller(9) and the footer too. slay, periodt, bye πŸŽ€πŸŒŸ

πŸ“¦ where this page comes from