STRUCT DENALI_CONTROLLER(9)
π struct denali_controller(9) π
okay so bestie, this is a page from the Kernel API Manual and it's all about struct denali_controller β the Denali NAND controller data. genuinely iconic little struct, let's get into it π«Ά
β¨ NAME β¨
struct denali_controller β Denali NAND controller data, no cap π
π¦ SYNOPSIS π¦
struct denali_controller {
struct nand_controller controller;
struct device *dev;
struct list_head chips;
unsigned long clk_rate;
unsigned long clk_x_rate;
void __iomem *reg;
void __iomem *host;
struct completion complete;
int irq;
u32 irq_mask;
u32 irq_status;
spinlock_t irq_lock;
bool dma_avail;
int devs_per_cs;
int oob_skip_bytes;
int active_bank;
int nbanks;
unsigned int revision;
unsigned int caps;
const struct nand_ecc_caps *ecc_caps;
u32 (*host_read)(struct denali_controller *denali, u32 addr);
void (*host_write)(struct denali_controller *denali, u32 addr, u32
data);
void (*setup_dma)(struct denali_controller *denali, dma_addr_t
dma_addr, int page, bool write);
};
like, look at all those fields, she's serving range πβ¨
π MEMBERS π
bestie, every single one, in order, let's go πββοΈπ¨
controllerβ the base NAND controller structure, the main character energy right at the top πdevβ the device πΈchipsβ the list of chips attached to this controller, her little squad fr frclk_rateβ frequency of core clock β°clk_x_rateβ frequency of bus interface clock, yes there's a second clock, she's got layers π¦regβ base of Register Interfacehostβ base of Host Data/Command interfacecompleteβ completion used to wait for interrupts, lowkey just sitting there waiting for a text back πirqβ interrupt numberirq_maskβ interrupt bits the controller is waiting forirq_statusβ interrupt bits of events that have happened, the receipts πirq_lockβ lock to protectirq_maskandirq_status, keep those two safe bestie πdma_availβ set if DMA engine is available βdevs_per_csβ number of devices connected in paralleloob_skip_bytesβ number of bytes in OOB skipped by the ECC engineactive_bankβ active bank id π¦nbanksβ the number of banks supported by this controllerrevisionβ IP revisioncapsβ controller capabilities that cannot be detected run-time πecc_capsβ ECC engine capabilities β¨host_readβ callback for read access of Host Data/Command Interfacehost_writeβ callback for write access of Host Data/Command Interfacesetup_dmaβ callback for setup of the Data DMA π₯
π SEE ALSO π
go check out the Kernel file ./drivers/mtd/nand/raw/denali.h, plus struct denali_chip_sel(9) and struct denali_chip(9) β they're all in the ./drivers/mtd/nand/raw directory and honestly they ate π
β¨
ngl bestie, this whole page lives under ./drivers/mtd/nand/raw β that's the neighborhood π‘
okay that's the whole thing, ily, go read the source π«Άπ
β sourced from ./drivers/mtd/nand/raw, dated October 2026, with the header calling it struct denali_controller(9) and the footer too. slay, periodt, bye ππ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms