STRUCT DDIV_CLK(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… struct ddiv_clk(9) β€” straight from the Kernel API Manual ✨

okay bestie, buckle up, because today we're getting into struct ddiv_clk β€” the DDIV clock. yes it's a struct, yes it's tiny, yes it still ate πŸ’… let's go.


🌸 NAME 🌸

struct ddiv_clk β€” the DDIV clock. that's it, that's the vibe. short, iconic, no notes πŸŽ€


✨ SYNOPSIS ✨

here's the whole shape of her, copy-pasted exactly, no cap:

struct ddiv_clk {
    struct rzv2h_cpg_priv *priv;
    struct clk_divider div;
    u8 mon;
 };

like… three members. minimalism is the moment πŸ¦‹


🫢 Members 🫢

okay so each of these little fields is doing its own main character thing:

  • priv β€” the CPG private data πŸ’– that's your backstage pass, the private stuff this clock is holding onto.
  • div β€” the divider clk πŸ”₯ literally the clock divider, living its life inside this struct.
  • mon β€” the monitor bit in the CPG_CLKSTATUS0 register πŸ‘€ yes, a u8, yes, it's watching, that's the whole job.
ngl bestie, that's genuinely the entire struct. no hidden lore. every field accounted for 🌈

πŸ‘‘ SEE ALSO πŸ‘‘

if you're the kind of person who clicks every link (respect, honestly), here's the full reading list. kernel file ./drivers/clk/renesas/rzv2h-cpg.c and friends β€” all of them, no skipping πŸ™ˆ:

  • struct rzv2h_pll_dsi_info(9)
  • struct rzv2h_cpg_priv(9)
  • struct mod_clock(9)
  • struct rzv2h_ff_mod_status_clk(9)
  • struct rzv2h_plldsi_div_clk(9)
  • struct rzv2h_plldsi_mux_clk(9)
  • struct rzv2h_cpg_pd(9)

and of course the source file itself, ./drivers/clk/renesas/rzv2h-cpg.c, which is where all of this actually lives πŸ“


that's the page, bestie β€” go read the source, it's giving documentation energy fr fr 🧚

sign-off time πŸ’œ: this lil beauty came out of ./drivers/clk/renesas, dated October 2026. screenshot it, frame it, cite it in your patch. periodt ⭐

πŸ“¦ where this page comes from