STRUCT CXL_PORT(9)

💖 struct cxl_port(9) 💖

okay so this is a page from the Kernel API Manual, and honestly? it's a glow-up. buckle up bestie, we're gonna meet struct cxl_port 🎀

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✨ NAME ✨

struct cxl_port — a logical collection of upstream port devices and downstream port devices, all so we can construct a CXL memory decode hierarchy. it's giving "found family, but make it hardware" 🫶

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🌸 SYNOPSIS 🌸

struct cxl_port {
    struct device dev;
    struct device *uport_dev;
    struct device *host_bridge;
    int id;
    struct xarray dports;
    struct xarray endpoints;
    struct xarray regions;
    struct cxl_dport *parent_dport;
    struct ida decoder_ida;
    struct cxl_register_map reg_map;
    struct cxl_component_regs regs;
    int nr_dports;
    int hdm_end;
    int commit_end;
    bool dead;
    unsigned int depth;
    struct cxl_cdat {
      void *table;
      size_t length;
    } cdat;
    bool cdat_available;
    long pci_latency;
    resource_size_t component_reg_phys;
 };

like, look at all those little guys. no cap, every single one matters 💅

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🦋 MEMBERS 🦋

here's the whole roster, and yes we're going through everybody, because nobody gets left out on my watch ✨

• dev — this port's device. the main character, lowkey 👑
• uport_dev — the PCI or platform device that implements the upstream port capability. it's the one actually doing the work behind the scenes, iykyk
• host_bridge — shortcut to the platform attach point for this port 🫶
• id — the id for the port device-name. name tag energy 🏷️
• dports — the cxl_dport instances referenced by decoders
• endpoints — cxl_ep instances, aka the endpoints that are a descendant of this port 🌈
• regions — cxl_region_ref instances, aka the regions mapped by this port
• parent_dport — the dport that points to this port in the parent. it's giving "who's your parent" 💀
• decoder_ida — allocator for decoder ids
• reg_map — component and ras register mapping parameters
• regs — mapped component registers
• nr_dports — number of entries in dports. literally just a count, bestie 🔢
• hdm_end — tracks the last allocated HDM decoder instance, for allocation ordering
• commit_end — cursor to track the highest committed decoder, for commit ordering
• dead — the last ep has been removed, so force port re-creation. dramatic? yes. necessary? also yes 😭
• depth — how deep this port is relative to the root. depth 0 is the root, so the root is the one sitting at the top of the group chat 💅
• cdat — cached CDAT data
• cdat_available — whether a CDAT attribute should be available in sysfs
• pci_latency — upstream latency in picoseconds
• component_reg_phys — physical address of the component register

ngl, dead is my favorite member name. imagine a struct just having a field called dead. iconic. no notes. 🔥

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🌟 SEE ALSO 🌟

• kernel file ./drivers/cxl/cxl.h
• cxl objects(9)
• struct cxl_decoder(9)
• struct cxl_endpoint_decoder(9)
• struct cxl_switch_decoder(9)
• struct cxl_rd_ops(9)
• struct cxl_root_decoder(9)
• struct cxl_region_params(9)
• struct cxl_region(9)
• struct cxl_root(9)
• struct cxl_dport(9)
• struct cxl_ep(9)
• struct cxl_region_ref(9)
• struct cxl_endpoint_dvsec_info(9)

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and that's the whole page, bestie 💖 before you go: this lil masterpiece came out of ./drivers/cxl and it's dated October 2026 — so like, future vibes fr fr. slay, go read some kernel headers 🌸✨🦋