STRUCT CXL_HDM(9)

✨ NAME ✨

okay so this is struct cxl_hdm(9) from the Kernel API Manual — and bestie, it's literally the HDM Decoder registers + cached / decoded capabilities. main character struct energy fr fr 💖

struct cxl_hdm — HDM Decoder registers and cached / decoded capabilities. no cap, that's the whole vibe 🎀

🦋 SYNOPSIS 🦋

here's the shape, copied exactly because we do not mess with source code 💅

struct cxl_hdm {
    struct cxl_component_regs regs;
    int decoder_count;
    unsigned int target_count;
    unsigned int interleave_mask;
    unsigned long iw_cap_mask;
    struct cxl_port *port;
 };

💅 Members 💅

• regs — mapped registers, see devm_cxl_setup_hdm. ✨
• decoder_count — number of decoders for this port. 🔥
• target_count — for switch decoders, max downstream port targets. 🎯
• interleave_mask — interleave granularity capability, see check_interleave_cap. 🧚
• iw_cap_mask — bitmask of supported interleave ways, see check_interleave_cap. 🌈
• port — mapped cxl_port, see devm_cxl_setup_hdm. 🫶

🌈 SEE ALSO 🌈

go peek at the kernel file ./drivers/cxl/cxlmem.h and these besties:

• struct cxl_memdev(9)
• struct cxl_attach_region(9)
• struct cxl_event_state(9)
• struct cxl_poison_state(9)
• struct cxl_fw_state(9)
• struct cxl_security_state(9)
• struct cxl_memdev_state(9)
• struct cxl_mem_command(9)

mwah 💋 source/version is ./drivers/cxl, date is October 2026 — ty for reading, bestie, you ate 🫶👑