STRUCT CXL_DPORT(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– struct cxl_dport(9) πŸ’–

okay bestie, welcome to the Kernel API Manual β€” we’re looking at the CXL downstream port struct, and it’s lowkey iconic. no cap, every field is here. πŸ’…


✨ NAME ✨

struct cxl_dport β€” a CXL downstream port, periodt.


πŸŽ€ SYNOPSIS πŸŽ€

struct cxl_dport {
    struct device *dport_dev;
    struct cxl_register_map reg_map;
    int port_id;
    struct cxl_rcrb_info rcrb;
    bool rch;
    struct cxl_port *port;
    struct cxl_regs regs;
    struct access_coordinate coord[ACCESS_COORDINATE_MAX];
    long link_latency;
    int gpf_dvsec;
};

πŸ’… Members πŸ’…

okay so these are the fields, and we are not skipping any of them. main character energy only. 🌟

  • dport_dev β€” PCI bridge or firmware device representing the downstream link. literally the device vibe check for the link.
  • reg_map β€” component and ras register mapping parameters. the mapping details live here, bestie.
  • port_id β€” unique hardware identifier for dport in decoder target list. it’s giving β€œI know exactly which port I am.” πŸ”₯
  • rcrb β€” Data about the Root Complex Register Block layout. yes, all the layout info. πŸŽ€
  • rch β€” Indicate whether this dport was enumerated in RCH or VH mode. tiny bool, big β€œwhich mode was I in?” energy.
  • port β€” reference to cxl_port that contains this downstream port. it points back to its port parent, slay. 🫢
  • regs β€” Dport parsed register blocks. parsed and present. ✨
  • coord β€” access coordinates (bandwidth and latency performance attributes). performance attributes stored in an array, iykyk.
  • link_latency β€” calculated PCIe downstream latency. the latency math has already been done, no stress. πŸ’œ
  • gpf_dvsec β€” Cached GPF port DVSEC. cached, cute, done. πŸ¦‹

🌈 SEE ALSO 🌈

peep these, bestie β€” the whole friend group is here:

  • Kernel file ./drivers/cxl/cxl.h
  • cxl objects(9)
  • struct cxl_decoder(9)
  • struct cxl_endpoint_decoder(9)
  • struct cxl_switch_decoder(9)
  • struct cxl_rd_ops(9)
  • struct cxl_root_decoder(9)
  • struct cxl_region_params(9)
  • struct cxl_region(9)
  • struct cxl_port(9)
  • struct cxl_root(9)
  • struct cxl_ep(9)
  • struct cxl_region_ref(9)
  • struct cxl_endpoint_dvsec_info(9)

signed off from ./drivers/cxl, dated October 2026 β€” mwah, kisses, go be iconic with your downstream ports πŸ’‹πŸŒΈ

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