STRUCT CS4270_MODE_RATIOS(9)

๐Ÿ“ฆ version 7.3.1, in nixpkgs unstable

โœจ struct cs4270_mode_ratios(9) โœจ

okay so bestie, welcome to the kernel API manual ๐Ÿ’… โ€” today we're looking at struct cs4270_mode_ratios, and honestly? it's giving "small struct, big responsibilities." no cap.


๐ŸŽ€ NAME ๐ŸŽ€

struct cs4270_mode_ratios โ€” clock ratio tables, fr fr ๐Ÿ•ฐ๏ธโœจ


๐Ÿฆ‹ SYNOPSIS ๐Ÿฆ‹

struct cs4270_mode_ratios {
    unsigned int ratio;
    u8 speed_mode;
    u8 mclk;
 };

like, that's the whole struct. three fields. iconic minimalism ๐Ÿ’œ


๐ŸŒธ Members ๐ŸŒธ

  • ratio โ€” the ratio of MCLK to the sample rate. it's literally the math-y one ๐Ÿงฎ
  • speed_mode โ€” the Speed Mode bits you gotta set in the Mode Control register for this ratio ๐Ÿ”ฅ
  • mclk โ€” the Ratio Select bits to set in the Mode Control register for this ratio ๐ŸŽฏ

๐Ÿ‘‘ Description ๐Ÿ‘‘

okay so the data for this chart is taken from Table 5 of the CS4270 reference manual โ€” so like, not us making it up, that's canon ๐Ÿ“–โœจ

This table is used to determine how to program the Mode Control register. It's also used by cs4270_set_dai_sysclk to tell ALSA which sampling rates the CS4270 currently supports. so yeah, it's double-booked and it's thriving ๐Ÿซถ

  • speed_mode is the corresponding bit pattern to be written to the MODE bits of the Mode Control Register
  • mclk is the corresponding bit pattern to be wirten to the MCLK bits of the Mode Control Register.
ngl that "wirten" is a typo that lives in the source and I'm not fixing it, we respect our elders ๐Ÿ™ˆ (also written, bestie, it means written ๐Ÿ’€)

In situations where a single ratio is represented by multiple speed modes, we favor the slowest speed. E.g, for a ratio of 128, we pick double-speed instead of quad-speed. lowkey a whole lifestyle choice โ€” slow and steady, main character energy ๐Ÿขโœจ However, the CS4270 errata states that divide-By-1.5 can cause failures, so we avoid that mode where possible. ๐Ÿšจ

Errata: There is an errata for the CS4270 where divide-by-1.5 does not work if Vd is 3.3V. If this effects you, select the CONFIG_SND_SOC_CS4270_VD33_ERRATA Kconfig option, and the driver will never select any sample rates that require divide-by-1.5. like, ever. periodt. ๐Ÿ’…โš ๏ธ

๐ŸŒˆ SEE ALSO ๐ŸŒˆ

Kernel file ./sound/soc/codecs/cs4270.c plus the whole friend group:


and that's the page!! ๐Ÿ“ this lil love letter to the CS4270 lives in ./sound/soc/codecs, dated October 2026, and it's part of the Kernel API Manual โ€” stay hydrated, read your errata, and slay your Mode Control register ๐Ÿ’–๐ŸŽ€๐Ÿ’…

๐Ÿ“ฆ where this page comes from