STRUCT CRYSTALCOVE_GPIO(9)

✨ struct crystalcove_gpio(9) ✨

okay so bestie, this is a page out of the Kernel API Manual — we're talking the struct crystalcove_gpio, aka the Crystal Cove GPIO controller 💅. It's a struct, it's got members, it's giving "small but mighty driver bookkeeping" energy. Let's get into it 🫶

🌸 NAME 🌸

struct crystalcove_gpio — the Crystal Cove GPIO controller 🎀 like, that's the whole vibe. It's the struct that holds the controller's state. Obsessed.

🦋 SYNOPSIS 🦋

struct crystalcove_gpio {
    struct mutex buslock;
    struct gpio_chip chip;
    struct regmap *regmap;
    int update;
    int intcnt_value;
    bool set_irq_mask;
 };

look at her. six members. absolutely iconic layout ngl ✨

👑 Members 👑

• buslock — this one's for bus lock/sync and unlock 🔒. It's the mutex doing the "one at a time please" thing so nobody clobbers anybody. periodt.
• chip — the abstract gpio_chip structure 💫. The generic, platonic-ideal version of a GPIO chip — the real one lives here, iykyk.
• regmap — the regmap that comes from the parent device 🌈. That's where the register access actually happens.
• update — pending IRQ setting update 🔥, which is going to be written to the chip upon unlock. So it's queued up, just chilling, waiting for its moment. main character energy honestly.
• intcnt_value — the Interrupt Detect value to be written 💖. That's the number that's gonna get pushed out when the time comes.
• set_irq_mask — true if the IRQ mask needs to be set, false to clear it 🙈. Binary queen. No in-between.

lowkey a lot of these fields only make sense together — update waits for the unlock, intcnt_value gets written, set_irq_mask decides set-vs-clear. Teamwork fr fr 🧚

⭐ SEE ALSO ⭐

• Kernel file ./drivers/gpio/gpio-crystalcove.c — go read the source bestie, that's where all the actual behaviour lives 💀

and that's the whole page!! no cap, that's it. this gem comes to you from ./drivers/gpio and it's dated October 2026 🌸 mwah, go forth and GPIO responsibly 💜🦋✨