STRUCT CLK_RCG(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– NAME πŸ’–

struct clk_rcg β€” the root clock generator, and yes bestie it's exactly as main-character as it sounds πŸ‘‘

okay so real quick before we dive in: this page is struct clk_rcg(9) from the Kernel API Manual, that's the title + the manual section, and it's all about this one struct. let's get into it 🫢


✨ SYNOPSIS ✨

struct clk_rcg {
    u32 ns_reg;
    u32 md_reg;
    struct mn       mn;
    struct pre_div  p;
    struct src_sel  s;
    const struct freq_tbl   *freq_tbl;
    struct clk_regmap       clkr;
 };

no cap, that's the whole shape of it. now let's do a vibe check on every single member, one by one, because we do not skip πŸ’…

πŸŽ€ Members πŸŽ€

  • ns_reg β€” the NS register. that's it, that's the whole gig ✨
  • md_reg β€” the MD register. iconic, separate register, separate slay πŸ’œ
  • mn β€” the mn counter πŸŒ€
  • p β€” the pre divider. lowkey doing the dividing before the dividing 🌸
  • s β€” the source selector. it picks where the source comes from, fr fr πŸ¦‹
  • freq_tbl β€” the frequency table. pointer to const struct freq_tbl, and this is where the frequencies live πŸ“Š
  • clkr β€” the regmap clock handle. the actual clock-y bit πŸ•
ngl the member list is short but every one of them is carrying the whole struct on its back, no notes πŸ’€

πŸ‘‘ SEE ALSO πŸ‘‘

  • the Kernel file ./drivers/clk/qcom/clk-rcg.h β€” go read it, iykyk πŸ“
  • struct mn(9)
  • struct pre_div(9)
  • struct src_sel(9)
  • struct clk_dyn_rcg(9)
  • struct clk_rcg2(9)

like literally the whole friend group right there 🧚


and that's the page!! πŸŽ€ this came to you from ./drivers/clk/qcom, dated October 2026, and it's struct clk_rcg(9) obvi πŸ’– go be iconic with your root clock generator, bestie 🌈⭐

πŸ“¦ where this page comes from