STRUCT CLK_PLL_DATA(9)

🌸 NAME 🌸

okay so this is the Kernel API Manual page for struct clk_pll_data, and the NAME line says struct clk_pll_data - pll data structure — literally the pll data structure bestie ✨.

✨ SYNOPSIS ✨

struct clk_pll_data {
    bool has_pllctrl;
    u32 phy_pllm;
    u32 phy_pll_ctl0;
    void __iomem *pllm;
    void __iomem *pllod;
    void __iomem *pll_ctl0;
    u32 pllm_lower_mask;
    u32 pllm_upper_mask;
    u32 pllm_upper_shift;
    u32 plld_mask;
    u32 clkod_mask;
    u32 clkod_shift;
    u32 postdiv;
};

🎀 Members 🎀

• has_pllctrl — if it's set to non zero, the lower 6 bits of the multiplier are in the pllm register of the pll controller; otherwise it is in pll_ctrl0((bit 11-6) (yep, the original punctuation is giving (( energy 😭 — the bit range is 11-6).
• phy_pllm — physical address of PLLM in the pll controller. Used when has_pllctrl is non zero. periodt.
• phy_pll_ctl0 — physical address of PLL ctrl0. This could be that of Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL or PA PLL available on keystone2. These PLLs are controlled by this register. Main PLL is controlled by a PLL controller. slay.
• pllm — PLL register map address for multiplier bits.
• pllod — PLL register map address for post divider bits.
• pll_ctl0 — PLL controller map address.
• pllm_lower_mask — multiplier lower mask.
• pllm_upper_mask — multiplier upper mask.
• pllm_upper_shift — multiplier upper shift.
• plld_mask — divider mask.
• clkod_mask — output divider mask.
• clkod_shift — output divider shift.
• postdiv — fixed post divider.

🌈 SEE ALSO 🌈

okay these are the linked-up friends, all from the kernel file ./drivers/clk/keystone/pll.c:

• struct clk_pll(9)
• _of_pll_clk_init(9)
• of_keystone_pll_clk_init(9)
• of_keystone_main_pll_clk_init(9)
• of_pll_div_clk_init(9)
• of_pll_mux_clk_init(9)

xoxo, this cutie is from ./drivers/clk/keystone, dated October 2026, and the page is struct clk_pll_data(9). bye bestie, stay slay 💅🫶💖