STRUCT CLK_PLL(9)

🌸 NAME 🌸

okay bestie, welcome to the struct clk_pll(9) page from the Kernel API Manual 💖 this one is short and sweet: it's literally a struct clk_pll — aka a phase locked loop (PLL) ✨

✨ SYNOPSIS ✨

here's the whole struct, every field exactly where it belongs, no edits from me 💅

struct clk_pll {
    u32 l_reg;
    u32 m_reg;
    u32 n_reg;
    u32 config_reg;
    u32 mode_reg;
    u32 status_reg;
    u8 status_bit;
    u8 post_div_width;
    u8 post_div_shift;
    const struct pll_freq_tbl *freq_tbl;
    struct clk_regmap clkr;
 };

👑 Members 👑

these are the member glow-ups the page actually tells you about:

• l_reg — L register. that's it, that's the vibe 🎀
• m_reg — M register. slay 💅
• n_reg — N register. iconic ✨
• config_reg — config register. yes bestie, the config one 🔧
• mode_reg — mode register. mode moment 🌈
• status_reg — status register. status check 👀
• status_bit — this bit gets ANDed with status_reg to determine if PLL is enabled — literally the little status vibe check 🔍
• freq_tbl — PLL frequency table. main character data fr fr 📊

tiny heads-up: the struct code also has post_div_width and post_div_shift chillin' in it, but the Members section gives them no description, so I'm not inventing any lore 🙈

🦋 SEE ALSO 🦋

• Kernel file ./drivers/clk/qcom/clk-pll.h — go peek at the source, iykyk 👀
• struct pll_freq_tbl(9) — another page to pull up, no cap 📖

mwah 💋 — this has been your struct clk_pll(9) moment, sourced from ./drivers/clk/qcom, dated October 2026. bye bestie 🫶